Intel® 64 and IA-32 Architectures Optimization Reference Manual

INTEL® 64 AND IA-32 PROCESSOR ARCHITECTURESµops. The remaining two decoders each decode a one µop instruction in each clockcycle.The front end can issue multiple µops per cycle, in original program order, to the outof-ordercore.The Intel Pentium M processor incorporates sophisticated branch prediction hardwareto support the out-of-order core. The branch prediction hardware includesdynamic prediction, and branch target buffers.The Intel Pentium M processor has enhanced dynamic branch prediction hardware.Branch target buffers (BTB) predict the direction and target of branches based on aninstruction’s address.The Pentium M Processor includes two techniques to reduce the execution time ofcertain operations:• ESP folding — This eliminates the ESP manipulation μops in stack-relatedinstructions such as PUSH, POP, CALL and RET. It increases decode rename andretirement throughput. ESP folding also increases execution bandwidth byeliminating µops which would have required execution resources.• Micro-ops (µops) fusion — Some of the most frequent pairs of µops derivedfrom the same instruction can be fused into a single µops. The followingcategories of fused µops have been implemented in the Pentium M processor:— “Store address” and “store data” μops are fused into a single “Store” μop.This holds for all types of store operations, including integer, floating-point,MMX technology, and Streaming SIMD Extensions (SSE and SSE2)operations.— A load μop in most cases can be fused with a successive execution μop.Thisholds for integer, floating-point and MMX technology loads and for most kindsof successive execution operations. Note that SSE Loads can not be fused.2.3.2 Data PrefetchingThe Intel Pentium M processor supports three prefetching mechanisms:• The first mechanism is a hardware instruction fetcher and is described in theprevious section.• The second mechanism automatically fetches data into the second-level cache.The implementation of automatic hardware prefetching in Pentium M processorfamily is basically similar to those described for NetBurst microarchitecture. Thetrigger threshold distance for each relevant processor models is shown inTable 2-6. The third mechanism is a software mechanism that fetches data intothe caches using the prefetch instructions.2-34