Intel® 64 and IA-32 Architectures Optimization Reference Manual

OPTIMIZING FOR SIMD INTEGER APPLICATIONSExample 5-36. Video Processing Using LDDQU to Avoid Cache Line Splits// Average half-pels horizontally (on // the “x” axis),// from one reference frame only.nextLinesLoop:lddqu xmm0, XMMWORD PTR [edx] // may not be 16B alignedlddqu xmm0, XMMWORD PTR [edx+1]lddqu xmm1, XMMWORD PTR [edx+eax]lddqu xmm1, XMMWORD PTR [edx+eax+1]pavgbxmm0, xmm1pavgbxmm2, xmm3movdqaXMMWORD PTR [ecx], xmm0 //results stored elsewheremovdqaXMMWORD PTR [ecx+eax], xmm2// (repeat ...)5.7.2 Increasing Bandwidth of Memory Fills and Video FillsIt is beneficial to understand how memory is accessed and filled. A memory-tomemoryfill (for example a memory-to-video fill) is defined as a 64-byte (cache line)load from memory which is immediately stored back to memory (such as a videoframe buffer).The following are guidelines for obtaining higher bandwidth and shorter latencies forsequential memory fills (video fills). These recommendations are relevant for all Intelarchitecture processors with MMX technology and refer to cases in which the loadsand stores do not hit in the first- or second-level cache.5.7.2.1 Increasing Memory Bandwidth Using the MOVDQ InstructionLoading any size data operand will cause an entire cache line to be loaded into thecache hierarchy. Thus, any size load looks more or less the same from a memorybandwidth perspective. However, using many smaller loads consumes more microarchitecturalresources than fewer larger stores. Consuming too many resources cancause the processor to stall and reduce the bandwidth that the processor can requestof the memory subsystem.Using MOVDQ to store the data back to UC memory (or WC memory in some cases)instead of using 32-bit stores (for example, MOVD) will reduce by three-quarters thenumber of stores per memory fill cycle. As a result, using the MOVDQ in memory fillcycles can achieve significantly higher effective bandwidth than using MOVD.5-35