Intel® 64 and IA-32 Architectures Optimization Reference Manual

USING PERFORMANCE MONITORING EVENTSMetricSpeculative TC-Delivered UopsTable B-3. Performance Metrics - Trace Cache and Front End (Contd.)Speculative MicrocodeμopsDescriptionNumber of speculativeμops originating whenthe TC is in delivermodeNumber of speculativeμops originating fromthe microcode ROMNot all μops of aninstruction from themicrocode ROM will beincluded.Event Name or MetricExpressionμop_queue_writesμop_queue_writesEvent Mask ValueRequiredFROM_TC_DELIVERFROM_ROMTable B-4. Performance Metrics - MemoryMetric Description Event Name or MetricExpressionPage Walk DTLB AllMisses1st Level Cache LoadMisses Retired2nd Level Cache LoadMisses RetiredDTLB Load MissesRetiredNumber of page walkrequests due to DTLBmisses from eitherload or storeNumber of retiredμops that experienced1st Level cache loadmisses.This stat is often usedin a per-instructionratio.Number of retired loadμops that experienced2nd Level cachemissesThis stat is known toundercount whenloads are spaced apart.Number of retired loadμops that experiencedDTLB missespage_walk_typeReplay_event; set thefollowing replay tag:1stL_cache_load_miss_retiredReplay_event; set thefollowing replay tag:2ndL_cache_load_miss_retiredReplay_event; set thefollowing replay tag:DTLB_load_miss_retiredEvent Mask ValueRequiredDTMISSNBOGUSNBOGUSNBOGUSB-12