IntelÂ® 64 and IA-32 Architectures Optimization Reference Manual

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MULTICORE AND HYPER-THREADING TECHNOLOGYUser/Source Coding Rule 32. (H impact, M generality) Minimize the sharing ofdata between threads that execute on different bus agents sharing a common bus.The situation of a platform consisting of multiple bus domains should also minimizedata sharing across bus domains.One technique to minimize sharing of data is to copy data to local stack variables if itis to be accessed repeatedly over an extended period. If necessary, results frommultiple threads can be combined later by writing them back to a shared memorylocation. This approach can also minimize time spent to synchronize access to shareddata.8.6.2.2 Batched Producer-Consumer ModelThe key benefit of a threaded producer-consumer design, shown in Figure 8-5, is tominimize bus traffic while sharing data between the producer and the consumerusing a shared second-level cache. On an Intel Core Duo processor and when thework buffers are small enough to fit within the first-level cache, re-ordering ofproducer and consumer tasks are necessary to achieve optimal performance. This isbecause fetching data from L2 to L1 is much faster than having a cache line in onecore invalidated and fetched from the bus.Figure 8-5 illustrates a batched producer-consumer model that can be used to overcomethe drawback of using small work buffers in a standard producer-consumermodel. In a batched producer-consumer model, each scheduling quanta batches twoor more producer tasks, each producer working on a designated buffer. The numberof tasks to batch is determined by the criteria that the total working set be greaterthan the first-level cache but smaller than the second-level cache.MainThreadP(1) P(2) P(3) P(4) P(5)P(6)P: producerC: consumerC(1)C(2)C(3)C(4)Figure 8-5. Batched Approach of Producer Consumer Model8-28
MULTICORE AND HYPER-THREADING TECHNOLOGYExample 8-8 shows the batched implementation of the producer and consumerthread functions.Example 8-8. Batched Implementation of the Producer Consumer Threadsvoid producer_thread(){ int iter_num = workamount - batchsize;int mode1;for (mode1=0; mode1 < batchsize; mode1++){ produce(buffs[mode1],count); }}while (iter_num--){ Signal(&signal1,1);produce(buffs[mode1],count); // placeholder functionWaitForSignal(&end1);mode1++;if (mode1 > batchsize)mode1 = 0;}void consumer_thread(){ int mode2 = 0;int iter_num = workamount - batchsize;while (iter_num--){ WaitForSignal(&signal1);consume(buffs[mode2],count); // placeholder functionSignal(&end1,1);mode2++;if (mode2 > batchsize)mode2 = 0;}}for (i=0;i batchsize)mode2 = 0;}8-29
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NIntel® 64 and IA-32 Architectures
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CONTENTS2.3.1 Front End. . . . . .
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CONTENTS3.7 PREFETCHING . . . . . .
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CONTENTS5.7.2.1 Increasing Memory B
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CONTENTS9.5.3 Streaming Store Instr
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CONTENTSB.7.4.3B.7.4.4B.7.4.5B.7.4.
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CONTENTSExample 4-1. Identification
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CONTENTSExample 9-8. Using HW Prefe
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CONTENTSFigure 9-7. Cache Blocking
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CHAPTER 1INTRODUCTIONThe Intel® 64
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INTRODUCTION• Chapter 10: Power O
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CHAPTER 2INTEL ® 64 AND IA-32 PROC
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INTEL® 64 AND IA-32 PROCESSOR ARCH
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CHAPTER 3GENERAL OPTIMIZATION GUIDE
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GENERAL OPTIMIZATION GUIDELINESThe
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GENERAL OPTIMIZATION GUIDELINEScomp
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GENERAL OPTIMIZATION GUIDELINES•
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GENERAL OPTIMIZATION GUIDELINESExam
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GENERAL OPTIMIZATION GUIDELINESthro
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GENERAL OPTIMIZATION GUIDELINESAsse
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GENERAL OPTIMIZATION GUIDELINESBeca
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GENERAL OPTIMIZATION GUIDELINESInst
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GENERAL OPTIMIZATION GUIDELINESXOR
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GENERAL OPTIMIZATION GUIDELINESUse
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GENERAL OPTIMIZATION GUIDELINESMOVS
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GENERAL OPTIMIZATION GUIDELINESPack
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GENERAL OPTIMIZATION GUIDELINES3.5.
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GENERAL OPTIMIZATION GUIDELINESFor
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GENERAL OPTIMIZATION GUIDELINESAs a
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GENERAL OPTIMIZATION GUIDELINESTher
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GENERAL OPTIMIZATION GUIDELINES—
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GENERAL OPTIMIZATION GUIDELINESmore
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GENERAL OPTIMIZATION GUIDELINESrequ
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GENERAL OPTIMIZATION GUIDELINESpref
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GENERAL OPTIMIZATION GUIDELINESpref
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GENERAL OPTIMIZATION GUIDELINES—
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GENERAL OPTIMIZATION GUIDELINESTher
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GENERAL OPTIMIZATION GUIDELINESstat
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GENERAL OPTIMIZATION GUIDELINESexte
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GENERAL OPTIMIZATION GUIDELINESFor
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CODING FOR SIMD ARCHITECTURES4.1.1
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CODING FOR SIMD ARCHITECTURESSoftwa
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CODING FOR SIMD ARCHITECTURESTo use
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CODING FOR SIMD ARCHITECTURESExampl
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CODING FOR SIMD ARCHITECTURESmance
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CODING FOR SIMD ARCHITECTURESpurpos
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CODING FOR SIMD ARCHITECTURESIf the
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CODING FOR SIMD ARCHITECTURESExampl
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CODING FOR SIMD ARCHITECTURES• Us
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CODING FOR SIMD ARCHITECTURESpatter
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CODING FOR SIMD ARCHITECTURESmoves
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CODING FOR SIMD ARCHITECTURES4-28
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OPTIMIZING FOR SIMD INTEGER APPLICA
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OPTIMIZING CACHE USAGEis not reside
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OPTIMIZING CACHE USAGEExample 9-11.
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OPTIMIZING CACHE USAGETable 9-3. De
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OPTIMIZING CACHE USAGE• If a proc
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64-BIT MODE CODING GUIDELINESAssemb
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64-BIT MODE CODING GUIDELINESinstru
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64-BIT MODE CODING GUIDELINES9-6
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POWER OPTIMIZATION FOR MOBILE USAGE
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APPLICATION PERFORMANCE TOOLSThe /f
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APPLICATION PERFORMANCE TOOLSTable
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APPLICATION PERFORMANCE TOOLSA.1.6.
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APPLICATION PERFORMANCE TOOLSExampl
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APPLICATION PERFORMANCE TOOLSExampl
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APPLICATION PERFORMANCE TOOLSprogra
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APPLICATION PERFORMANCE TOOLSThe Li
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APPLICATION PERFORMANCE TOOLSA.5 IN
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USING PERFORMANCE MONITORING EVENTS
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INSTRUCTION LATENCY AND THROUGHPUTW
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INSTRUCTION LATENCY AND THROUGHPUTo
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INSTRUCTION LATENCY AND THROUGHPUT
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INSTRUCTION LATENCY AND THROUGHPUTC
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STACK ALIGNMENTThe solution to this
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STACK ALIGNMENTExample D-1. Aligned
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STACK ALIGNMENTExample D-2. Aligned
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STACK ALIGNMENTD-8
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SUMMARY OF RULES AND SUGGESTIONSret
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SUMMARY OF RULES AND SUGGESTIONSfou
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SUMMARY OF RULES AND SUGGESTIONSvar
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SUMMARY OF RULES AND SUGGESTIONSto
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SUMMARY OF RULES AND SUGGESTIONSCor
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SUMMARY OF RULES AND SUGGESTIONSE-1
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INDEXsummary of rules, E-1tuning hi
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INDEXevent ratios, B-50execution co
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INDEXprefetching, 8-5SFENCE instruc
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INDEXPMAXSW, 5-28PMAXUB, 5-28PMINSW
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INDEXIndex-10
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