Intel® 64 and IA-32 Architectures Optimization Reference Manual

OPTIMIZING FOR SIMD INTEGER APPLICATIONS5.7.2.2 Increasing Memory Bandwidth by Loading and Storing to andfrom the Same DRAM PageDRAM is divided into pages, which are not the same as operating system (OS) pages.The size of a DRAM page is a function of the total size of the DRAM and the organizationof the DRAM. Page sizes of several Kilobytes are common. Like OS pages, DRAMpages are constructed of sequential addresses. Sequential memory accesses to thesame DRAM page have shorter latencies than sequential accesses to different DRAMpages.In many systems the latency for a page miss (that is, an access to a different pageinstead of the page previously accessed) can be twice as large as the latency of amemory page hit (access to the same page as the previous access). Therefore, if theloads and stores of the memory fill cycle are to the same DRAM page, a significantincrease in the bandwidth of the memory fill cycles can be achieved.5.7.2.3 Increasing UC and WC Store Bandwidth by Using Aligned StoresUsing aligned stores to fill UC or WC memory will yield higher bandwidth than usingunaligned stores. If a UC store or some WC stores cross a cache line boundary, asingle store will result in two transaction on the bus, reducing the efficiency of thebus transactions. By aligning the stores to the size of the stores, you eliminate thepossibility of crossing a cache line boundary, and the stores will not be split into separatetransactions.5.8 CONVERTING FROM 64-BIT TO 128-BIT SIMDINTEGERSSSE2 defines a superset of 128-bit integer instructions currently available in MMXtechnology; the operation of the extended instructions remains. The superset simplyoperates on data that is twice as wide. This simplifies porting of 64-bit integer applications.However, there are few considerations:• Computation instructions which use a memory operand that may not be alignedto a 16-byte boundary must be replaced with an unaligned 128-bit load(MOVDQU) followed by the same computation operation that uses insteadregister operands.Use of 128-bit integer computation instructions with memory operands that arenot 16-byte aligned will result in a #GP. Unaligned 128-bit loads and stores arenot as efficient as corresponding aligned versions; this fact can reduce theperformance gains when using the 128-bit SIMD integer extensions.• General guidelines on the alignment of memory operands are:— The greatest performance gains can be achieved when all memory streamsare 16-byte aligned.5-36