Intel® 64 and IA-32 Architectures Optimization Reference Manual

INTEL® 64 AND IA-32 PROCESSOR ARCHITECTURES2.4.2 Data PrefetchingIntel Core Solo and Intel Core Duo processors provide hardware mechanisms toprefetch data from memory to the second-level cache. There are two techniques:1. One mechanism activates after the data access pattern experiences two cachereferencemisses within a trigger-distance threshold (see Table 2-6). Thismechanism is similar to that of the Pentium M processor, but can track 16 forwarddata streams and 4 backward streams.2. The second mechanism fetches an adjacent cache line of data after experiencinga cache miss. This effectively simulates the prefetching capabilities of 128-bytesectors (similar to the sectoring of two adjacent 64-byte cache lines available inPentium 4 processors).Hardware prefetch requests are queued up in the bus system at lower priority thannormal cache-miss requests. If bus queue is in high demand, hardware prefetchrequests may be ignored or cancelled to service bus traffic required by demandcache-misses and other bus transactions. Hardware prefetch mechanisms areenhanced over that of Pentium M processor by:• Data stores that are not in the second-level cache generate read for ownershiprequests. These requests are treated as loads and can trigger a prefetch stream.• Software prefetch instructions are treated as loads, they can also trigger aprefetch stream.2.5 INTEL ® HYPER-THREADING TECHNOLOGYIntel ® Hyper-Threading Technology (HT Technology) is supported by specificmembers of the Intel Pentium 4 and Xeon processor families. The technology enablessoftware to take advantage of task-level, or thread-level parallelism by providingmultiple logical processors within a physical processor package. In its first implementationin Intel Xeon processor, Hyper-Threading Technology makes a single physicalprocessor appear as two logical processors.The two logical processors each have a complete set of architectural registers whilesharing one single physical processor's resources. By maintaining the architecturestate of two processors, an HT Technology capable processor looks like two processorsto software, including operating system and application code.By sharing resources needed for peak demands between two logical processors, HTTechnology is well suited for multiprocessor systems to provide an additional performanceboost in throughput when compared to traditional MP systems.Figure 2-7 shows a typical bus-based symmetric multiprocessor (SMP) based onprocessors supporting HT Technology. Each logical processor can execute a softwarethread, allowing a maximum of two software threads to execute simultaneously onone physical processor. The two software threads execute simultaneously, meaningthat in the same clock cycle an “add” operation from logical processor 0 and another2-37