IntelÂ® 64 and IA-32 Architectures Optimization Reference Manual

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GENERAL OPTIMIZATION GUIDELINES3.5.4.1 Alternate Packing TechniquesThe packing method implemented in the reference code of Example 3-22 will experiencedelay as it assembles 4 doubleword result from memory into an XMM registerdue to store-forwarding restrictions.Three alternate techniques for packing, using different SIMD instruction to assemblecontents in XMM registers are shown in Example 3-23. All three techniques avoidstore-forwarding delay by satisfying the restrictions on data sizes between apreceding store and subsequent load operations.Example 3-23. Three Alternate Packing Methods for Avoiding Store Forwarding DifficultyPacking Method 1 Packing Method 2 Packing Method 3movd xmm0, [ebp+16+4]movd xmm1, [ebp+16+8]movd xmm2, [ebp+16+12]movd xmm3, [ebp+12+16+4]punpckldq xmm0, xmm1punpckldq xmm2, xmm3punpckldq xmm0, xmm2movd xmm0, [ebp+16+4]movd xmm1, [ebp+16+8]movd xmm2, [ebp+16+12]movd xmm3, [ebp+12+16+4]psllq xmm3, 32orps xmm2, xmm3psllq xmm1, 32orps xmm0, xmm1movlhpsxmm0, xmm2movd xmm0, [ebp+16+4]movd xmm1, [ebp+16+8]movd xmm2, [ebp+16+12]movd xmm3, [ebp+12+16+4]movlhps xmm1,xmm3psllq xmm1, 32movlhps xmm0, xmm2orps xmm0, xmm13.5.4.2 Simplifying Result PassingIn Example 3-22, individual results were passed to the packing stage by storing tocontiguous memory locations. Instead of using memory spills to pass four results,result passing may be accomplished by using either one or more registers. Usingregisters to simplify result passing and reduce memory spills can improve performanceby varying degrees depending on the register pressure at runtime.Example 3-24 shows the coding sequence that uses four extra XMM registers toreduce all memory spills of passing results back to the parent routine. However, softwaremust observe the following conditions when using this technique:• There is no register shortage.• If the loop does not have many stores or loads but has many computations, thistechnique does not help performance. This technique adds work to the computationalunits, while the store and loads ports are idle.3-42
GENERAL OPTIMIZATION GUIDELINESExample 3-24. Using Four Registers to Reduce Memory Spills and Simplify Result Passingmov eax, [ebp+4]mov [ebp], eaxcall foomovd xmm0, eaxmov eax, [ebp+8]mov [ebp], eaxcall foomovd xmm1, eaxmov eax, [ebp+12]mov [ebp], eaxcall foomovd xmm2, eaxmov eax, [ebp+12+4]mov [ebp], eaxcall foomovd xmm3, eax3-43
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NIntel® 64 and IA-32 Architectures
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CONTENTS2.3.1 Front End. . . . . .
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CONTENTS3.7 PREFETCHING . . . . . .
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CONTENTS5.7.2.1 Increasing Memory B
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CONTENTS9.5.3 Streaming Store Instr
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CONTENTSB.7.4.3B.7.4.4B.7.4.5B.7.4.
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CONTENTSExample 4-1. Identification
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CONTENTSExample 9-8. Using HW Prefe
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CONTENTSFigure 9-7. Cache Blocking
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CHAPTER 1INTRODUCTIONThe Intel® 64
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INTRODUCTION• Chapter 10: Power O
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CHAPTER 2INTEL ® 64 AND IA-32 PROC
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INTEL® 64 AND IA-32 PROCESSOR ARCH
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CODING FOR SIMD ARCHITECTURESTo use
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CODING FOR SIMD ARCHITECTURES4.3.1
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CODING FOR SIMD ARCHITECTURESExampl
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CODING FOR SIMD ARCHITECTURESmance
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CODING FOR SIMD ARCHITECTURESpurpos
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CODING FOR SIMD ARCHITECTURES4.4.3
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CODING FOR SIMD ARCHITECTURESIf the
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CODING FOR SIMD ARCHITECTURESExampl
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CODING FOR SIMD ARCHITECTURES• Us
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CODING FOR SIMD ARCHITECTURESpatter
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CODING FOR SIMD ARCHITECTURESmoves
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CODING FOR SIMD ARCHITECTURES4-28
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OPTIMIZING FOR SIMD INTEGER APPLICA
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OPTIMIZING FOR SIMD FLOATING-POINT
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MULTICORE AND HYPER-THREADING TECHN
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OPTIMIZING CACHE USAGE• Take adva
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OPTIMIZING CACHE USAGEHardware pref
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OPTIMIZING CACHE USAGEThe non-tempo
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OPTIMIZING CACHE USAGE9.5.1.3 Memor
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OPTIMIZING CACHE USAGENOTEFailure t
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OPTIMIZING CACHE USAGE9.5.5 CLFLUSH
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OPTIMIZING CACHE USAGE• The hardw
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OPTIMIZING CACHE USAGETimeExecution
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OPTIMIZING CACHE USAGEschedule pref
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OPTIMIZING CACHE USAGEtime is large
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OPTIMIZING CACHE USAGEresource stal
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OPTIMIZING CACHE USAGEPrefetchntaDa
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OPTIMIZING CACHE USAGEExample 9-7.
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OPTIMIZING CACHE USAGEA characteris
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OPTIMIZING CACHE USAGE9.7 MEMORY OP
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OPTIMIZING CACHE USAGE9.7.2.3 Concl
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OPTIMIZING CACHE USAGEis not reside
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OPTIMIZING CACHE USAGEExample 9-11.
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OPTIMIZING CACHE USAGETable 9-3. De
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OPTIMIZING CACHE USAGE• If a proc
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64-BIT MODE CODING GUIDELINESAssemb
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64-BIT MODE CODING GUIDELINESinstru
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64-BIT MODE CODING GUIDELINES9-6
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POWER OPTIMIZATION FOR MOBILE USAGE
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APPLICATION PERFORMANCE TOOLSThe /f
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APPLICATION PERFORMANCE TOOLSTable
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APPLICATION PERFORMANCE TOOLSA.1.6.
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APPLICATION PERFORMANCE TOOLSExampl
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APPLICATION PERFORMANCE TOOLSExampl
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APPLICATION PERFORMANCE TOOLSprogra
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APPLICATION PERFORMANCE TOOLSThe Li
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APPLICATION PERFORMANCE TOOLSA.5 IN
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USING PERFORMANCE MONITORING EVENTS
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INSTRUCTION LATENCY AND THROUGHPUTW
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INSTRUCTION LATENCY AND THROUGHPUTT
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INSTRUCTION LATENCY AND THROUGHPUT
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INSTRUCTION LATENCY AND THROUGHPUTC
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STACK ALIGNMENTThe solution to this
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STACK ALIGNMENTExample D-1. Aligned
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STACK ALIGNMENTExample D-2. Aligned
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STACK ALIGNMENTD-8
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SUMMARY OF RULES AND SUGGESTIONSret
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SUMMARY OF RULES AND SUGGESTIONSfou
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SUMMARY OF RULES AND SUGGESTIONSvar
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SUMMARY OF RULES AND SUGGESTIONSto
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SUMMARY OF RULES AND SUGGESTIONSCor
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SUMMARY OF RULES AND SUGGESTIONSE-1
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INDEXsummary of rules, E-1tuning hi
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INDEXevent ratios, B-50execution co
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INDEXprefetching, 8-5SFENCE instruc
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INDEXPMAXSW, 5-28PMAXUB, 5-28PMINSW
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INDEXIndex-10
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IntelÂ® 64 and IA-32 Architectures Optimization Reference Manual

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