Intel® 64 and IA-32 Architectures Optimization Reference Manual

INSTRUCTION LATENCY AND THROUGHPUTC.3 LATENCY AND THROUGHPUTThis section presents the latency and throughput information for commonly-usedinstructions including: MMX technology, Streaming SIMD Extensions, subsequentgenerations of SIMD instruction extensions, and most of the frequently used generalpurposeinteger and x87 floating-point instructions.Due to the complexity of dynamic execution and out-of-order nature of the executioncore, the instruction latency data may not be sufficient to accurately predict realisticperformance of actual code sequences based on adding instruction latency data.• Instruction latency data is useful when tuning a dependency chain. However,dependency chains limit the out-of-order core’s ability to execute micro-ops inparallel. Instruction throughput data are useful when tuning parallel codeunencumbered by dependency chains.• Numeric data in the tables is:— approximate and subject to change in future implementations of the microarchitecture.— not meant to be used as reference for instruction-level performancebenchmarks. Comparison of instruction-level performance of microprocessorsthat are based on different microarchitectures is a complex subjectand requires information that is beyond the scope of this manual.Comparisons of latency and throughput data between different microarchitecturescan be misleading.Appendix C.3.1 provides latency and throughput data for the register-to-registerinstruction type. Appendix C.3.3 discusses how to adjust latency and throughputspecifications for the register-to-memory and memory-to-register instructions.In some cases, the latency or throughput figures given are just one half of a clock.This occurs only for the double-speed ALUs.C.3.1Latency and Throughput with Register OperandsInstruction latency and throughput data are presented in Table C-1 throughTable C-10. Tables include Supplemental Streaming SIMD Extension 3, StreamingSIMD Extension 3, Streaming SIMD Extension 2, Streaming SIMD Extension, MMXtechnology and most common Intel 64 and IA-32 instructions. Instruction latencyand throughput for different processor microarchitectures are in separate columns.Processor instruction timing data may vary from one implementation to another.Intel 64 and IA-32 processors with different implementation characteristics can beidentified by the encoded values of “display_family” and “display_model”. The definitionsof “display_family” and “display_model” can be found in the reference pages ofCPUID (see Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume2A). The tables of instruction and latency data are grouped by an abbreviated formof hex values “DisplayFamilyValue_DisplayModelValue”. Processors based on IntelNetBurst microarchitecture has a “DisplayFamilyValue” of 0FH, “DisplayModelValue”C-3