IntelÂ® 64 and IA-32 Architectures Optimization Reference Manual

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OPTIMIZING FOR SIMD FLOATING-POINT APPLICATIONSxmm0xmm1xmm2xmm3A1 A2 A3 A4 B1 B2 B3 B4 C1 C2 C3 C4 D1 D2 D3 D4MOVLHPSMOVHLPSMOVLHPSMOVHLPSA1 A2 B1 B2 A3 A4 B3 B4 C1 C2 D1 D2 C3 C4 D3 D4ADDPSADDPSA1+A3 A2+A4 B1+B3 B2+B4 C1+C3 C2+C4 D1+D3 D2+D4SHUFPSSHUFPSA1+A3 B1+B3 C1+C3 D1+D3 A2+A4 B2+B4 C2+C4 D2+D4ADDPSA1+A2+A3+A4 B1+B2+B3+B4 C1+C2+C3+C4 D1+D2+D3+D4OM15169Figure 6-4. Horizontal Add Using MOVHLPS/MOVLHPSExample 6-9. Horizontal Add Using MOVHLPS/MOVLHPSvoid horiz_add(Vertex_soa *in, float *out) {__asm {mov ecx, in // load structure addressesmov edx, outmovaps xmm0, [ecx] // load A1 A2 A3 A4 => xmm0movaps xmm1, [ecx+16] // load B1 B2 B3 B4 => xmm1movaps xmm2, [ecx+<strong>32</strong>] // load C1 C2 C3 C4 => xmm2movaps xmm3, [ecx+48] // load D1 D2 D3 D4 => xmm36-14
OPTIMIZING FOR SIMD FLOATING-POINT APPLICATIONSExample 6-9. Horizontal Add Using MOVHLPS/MOVLHPS (Contd.)// START HORIZONTAL ADDmovaps xmm5, xmm0movlhps xmm5, xmm1movhlps xmm1, xmm0addps xmm5, xmm1movaps xmm4, xmm2movlhps xmm2, xmm3movhlps xmm3, xmm4addps xmm3, xmm2movaps xmm6, xmm3shufps xmm3, xmm5, 0xDDshufps xmm5, xmm6, 0x88addps xmm6, xmm5// END HORIZONTAL ADDmovaps [edx], xmm6}}// xmm5= A1,A2,A3,A4// xmm5= A1,A2,B1,B2// xmm1= A3,A4,B3,B4// xmm5= A1+A3,A2+A4,B1+B3,B2+B4// xmm2= C1,C2,D1,D2// xmm3= C3,C4,D3,D4// xmm3= C1+C3,C2+C4,D1+D3,D2+D4// xmm6= C1+C3,C2+C4,D1+D3,D2+D4//xmm6=A1+A3,B1+B3,C1+C3,D1+D3// xmm5= A2+A4,B2+B4,C2+C4,D2+D4// xmm6= D,C,B,AExample 6-10. Horizontal Add Using Intrinsics with MOVHLPS/MOVLHPSvoid horiz_add_intrin(Vertex_soa *in, float *out){__m128 v, v2, v3, v4;__m128 tmm0,tmm1,tmm2,tmm3,tmm4,tmm5,tmm6;// Temporary variablestmm0 = _mm_load_ps(in->x); // tmm0 = A1 A2 A3 A4tmm1 = _mm_load_ps(in->y); // tmm1 = B1 B2 B3 B4tmm2 = _mm_load_ps(in->z); // tmm2 = C1 C2 C3 C4tmm3 = _mm_load_ps(in->w); // tmm3 = D1 D2 D3 D4tmm5 = tmm0; // tmm0 = A1 A2 A3 A4tmm5 = _mm_movelh_ps(tmm5, tmm1); // tmm5 = A1 A2 B1 B2tmm1 = _mm_movehl_ps(tmm1, tmm0); // tmm1 = A3 A4 B3 B4tmm5 = _mm_add_ps(tmm5, tmm1); // tmm5 = A1+A3 A2+A4 B1+B3 B2+B4tmm4 = tmm2;6-15
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NIntel® 64 and IA-32 Architectures
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CONTENTS2.3.1 Front End. . . . . .
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CONTENTS3.7 PREFETCHING . . . . . .
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CONTENTS5.7.2.1 Increasing Memory B
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CONTENTS9.5.3 Streaming Store Instr
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CONTENTSB.7.4.3B.7.4.4B.7.4.5B.7.4.
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CONTENTSExample 4-1. Identification
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CONTENTSExample 9-8. Using HW Prefe
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CONTENTSFigure 9-7. Cache Blocking
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CHAPTER 1INTRODUCTIONThe Intel® 64
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INTRODUCTION• Chapter 10: Power O
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CHAPTER 2INTEL ® 64 AND IA-32 PROC
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INTEL® 64 AND IA-32 PROCESSOR ARCH
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CHAPTER 3GENERAL OPTIMIZATION GUIDE
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GENERAL OPTIMIZATION GUIDELINESThe
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GENERAL OPTIMIZATION GUIDELINEScomp
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GENERAL OPTIMIZATION GUIDELINES•
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GENERAL OPTIMIZATION GUIDELINESExam
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GENERAL OPTIMIZATION GUIDELINESthro
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GENERAL OPTIMIZATION GUIDELINESAsse
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GENERAL OPTIMIZATION GUIDELINESpred
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GENERAL OPTIMIZATION GUIDELINESIn t
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GENERAL OPTIMIZATION GUIDELINESBeca
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GENERAL OPTIMIZATION GUIDELINESInst
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GENERAL OPTIMIZATION GUIDELINESXOR
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GENERAL OPTIMIZATION GUIDELINESUse
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GENERAL OPTIMIZATION GUIDELINESMOVS
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GENERAL OPTIMIZATION GUIDELINESPack
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GENERAL OPTIMIZATION GUIDELINES3.5.
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GENERAL OPTIMIZATION GUIDELINESFor
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GENERAL OPTIMIZATION GUIDELINESAs a
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GENERAL OPTIMIZATION GUIDELINESTher
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GENERAL OPTIMIZATION GUIDELINES—
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GENERAL OPTIMIZATION GUIDELINESmore
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GENERAL OPTIMIZATION GUIDELINESrequ
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GENERAL OPTIMIZATION GUIDELINESmiss
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GENERAL OPTIMIZATION GUIDELINESpref
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GENERAL OPTIMIZATION GUIDELINESpref
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GENERAL OPTIMIZATION GUIDELINES—
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GENERAL OPTIMIZATION GUIDELINESTher
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GENERAL OPTIMIZATION GUIDELINESstat
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GENERAL OPTIMIZATION GUIDELINESexte
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GENERAL OPTIMIZATION GUIDELINESFor
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CODING FOR SIMD ARCHITECTURES4.1.1
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CODING FOR SIMD ARCHITECTURESSoftwa
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CODING FOR SIMD ARCHITECTURESTo use
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CODING FOR SIMD ARCHITECTURESExampl
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CODING FOR SIMD ARCHITECTURESmance
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CODING FOR SIMD ARCHITECTURESpurpos
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CODING FOR SIMD ARCHITECTURESIf the
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CODING FOR SIMD ARCHITECTURESExampl
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CODING FOR SIMD ARCHITECTURES• Us
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CODING FOR SIMD ARCHITECTURESpatter
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CODING FOR SIMD ARCHITECTURESmoves
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CODING FOR SIMD ARCHITECTURES4-28
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MULTICORE AND HYPER-THREADING TECHN
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MULTICORE AND HYPER-THREADING TECHN
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OPTIMIZING CACHE USAGE• Take adva
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OPTIMIZING CACHE USAGEHardware pref
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OPTIMIZING CACHE USAGEThe non-tempo
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OPTIMIZING CACHE USAGE9.5.1.3 Memor
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OPTIMIZING CACHE USAGENOTEFailure t
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OPTIMIZING CACHE USAGE9.5.5 CLFLUSH
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OPTIMIZING CACHE USAGE• The hardw
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OPTIMIZING CACHE USAGETimeExecution
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OPTIMIZING CACHE USAGEschedule pref
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OPTIMIZING CACHE USAGEtime is large
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OPTIMIZING CACHE USAGEresource stal
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OPTIMIZING CACHE USAGEPrefetchntaDa
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OPTIMIZING CACHE USAGEExample 9-7.
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OPTIMIZING CACHE USAGEA characteris
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OPTIMIZING CACHE USAGE9.7 MEMORY OP
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OPTIMIZING CACHE USAGE9.7.2.3 Concl
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OPTIMIZING CACHE USAGEis not reside
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OPTIMIZING CACHE USAGEExample 9-11.
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OPTIMIZING CACHE USAGETable 9-3. De
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OPTIMIZING CACHE USAGE• If a proc
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64-BIT MODE CODING GUIDELINESAssemb
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64-BIT MODE CODING GUIDELINESinstru
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64-BIT MODE CODING GUIDELINES9-6
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POWER OPTIMIZATION FOR MOBILE USAGE
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APPLICATION PERFORMANCE TOOLSThe /f
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APPLICATION PERFORMANCE TOOLSTable
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APPLICATION PERFORMANCE TOOLSA.1.6.
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APPLICATION PERFORMANCE TOOLSExampl
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APPLICATION PERFORMANCE TOOLSExampl
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APPLICATION PERFORMANCE TOOLSprogra
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APPLICATION PERFORMANCE TOOLSThe Li
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APPLICATION PERFORMANCE TOOLSA.5 IN
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USING PERFORMANCE MONITORING EVENTS
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INSTRUCTION LATENCY AND THROUGHPUTW
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INSTRUCTION LATENCY AND THROUGHPUTo
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INSTRUCTION LATENCY AND THROUGHPUTT
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INSTRUCTION LATENCY AND THROUGHPUT
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INSTRUCTION LATENCY AND THROUGHPUTC
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STACK ALIGNMENTThe solution to this
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STACK ALIGNMENTExample D-1. Aligned
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STACK ALIGNMENTExample D-2. Aligned
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STACK ALIGNMENTD-8
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SUMMARY OF RULES AND SUGGESTIONSret
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SUMMARY OF RULES AND SUGGESTIONSfou
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SUMMARY OF RULES AND SUGGESTIONSvar
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SUMMARY OF RULES AND SUGGESTIONSto
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SUMMARY OF RULES AND SUGGESTIONSCor
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SUMMARY OF RULES AND SUGGESTIONSE-1
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INDEXsummary of rules, E-1tuning hi
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INDEXevent ratios, B-50execution co
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INDEXprefetching, 8-5SFENCE instruc
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INDEXPMAXSW, 5-28PMAXUB, 5-28PMINSW
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INDEXIndex-10
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Intel Corp.999 CANADA PLACE,Suite 4
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IntelÂ® 64 and IA-32 Architectures Optimization Reference Manual

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