IntelÂ® 64 and IA-32 Architectures Optimization Reference Manual

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USING PERFORMANCE MONITORING EVENTSTable B-10. Metrics That Utilize the Execution Tagging Mechanism (Contd.)Execution Metric TagsScalar_DP_retired128_bit_MMX_retired64_bit_MMX_retiredX87_FP_retiredUpstream ESCRSet ALL bit in theevent mask andTagUop bit in theESCR ofscalar_DP_uop.Set ALL bit in theevent mask andTagUop bit in theESCR of128_bit_MMX_uop.Set ALL bit in theevent mask andTagUop bit in theESCR of64_bit_MMX_uop.Set ALL bit in theevent mask andTagUop bit in theESCR ofx87_FP_uop.Tag Value inUpstream ESCRSee Event MaskParameter forExecution_event1 NBOGUS01 NBOGUS01 NBOGUS01 NBOGUS0Table B-11. New Metrics for Pentium 4 Processor (Family 15, Model 3)MetricInstructions CompletedSpeculative Instructions CompletedDescriptionsNon-bogusinstructionscompleted andretiredNumber ofinstructionsdecoded andexecutedspeculativelyEvent Name orMetricExpressioninstr_completedinstr_completedEvent Mask valuerequiredNBOGUSBOGUSB-38
USING PERFORMANCE MONITORING EVENTSB.4 USING PERFORMANCE METRICS WITH HYPER-THREADING TECHNOLOGYOn Intel Xeon processors that support HT Technology, the performance metrics listedin Tables B-1 through B-7 may be qualified to associate the counts with a specificlogical processor, provided the relevant performance monitoring events supportsqualification by logical processor. Within the subset of those performance metrics thatsupport qualification by logical processors, some of them can be programmed withparallel ESCRs and CCCRs to collect separate counts for each logical processor simultaneously.For some metrics, qualification by logical processor is supported but thereis not sufficient number of MSRs for simultaneous counting of the same metric on bothlogical processors. In both cases, it is also possible to program the relevant ESCR fora performance metric that supports qualification by logical processor to producecounts that are, typically, the sum of contributions from both logical processors.A number of performance metrics are based on performance monitoring events thatdo not support qualification by logical processor. Any attempts to program the relevantESCRs to qualify counts by logical processor will not produce different results.The results obtained in this manner should not be summed together.The performance metrics listed in Tables B-1 through B-7 fall into three categories:• Logical processor specific and supporting parallel counting• Logical processor specific but constrained by ESCR limitations• Logical processor independent and not supporting parallel countingTable B-11 lists performance metrics in the first and second category. Table B-12 listsperformance metrics in the third category.There are four specific performance metrics related to the trace cache that areexceptions to the three categories above. They are:• Logical Processor 0 Deliver Mode• Logical Processor 1 Deliver Mode• Logical Processor 0 Build Mode• Logical Processor 0 Build ModeEach of these four metrics cannot be qualified by programming bit 0 to 4 in therespective ESCR. However, it is possible and useful to collect two of these fourmetrics simultaneously.B-39
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NIntel® 64 and IA-32 Architectures
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CONTENTS2.3.1 Front End. . . . . .
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CONTENTS3.7 PREFETCHING . . . . . .
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CONTENTS5.7.2.1 Increasing Memory B
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CONTENTS9.5.3 Streaming Store Instr
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CONTENTSB.7.4.3B.7.4.4B.7.4.5B.7.4.
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CONTENTSExample 4-1. Identification
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CONTENTSExample 9-8. Using HW Prefe
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CONTENTSFigure 9-7. Cache Blocking
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CHAPTER 1INTRODUCTIONThe Intel® 64
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INTRODUCTION• Chapter 10: Power O
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CHAPTER 2INTEL ® 64 AND IA-32 PROC
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INTEL® 64 AND IA-32 PROCESSOR ARCH
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CHAPTER 3GENERAL OPTIMIZATION GUIDE
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GENERAL OPTIMIZATION GUIDELINESThe
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GENERAL OPTIMIZATION GUIDELINEScomp
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GENERAL OPTIMIZATION GUIDELINES•
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GENERAL OPTIMIZATION GUIDELINESExam
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GENERAL OPTIMIZATION GUIDELINESthro
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GENERAL OPTIMIZATION GUIDELINESAsse
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GENERAL OPTIMIZATION GUIDELINESBeca
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GENERAL OPTIMIZATION GUIDELINESInst
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GENERAL OPTIMIZATION GUIDELINESXOR
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GENERAL OPTIMIZATION GUIDELINESUse
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GENERAL OPTIMIZATION GUIDELINESMOVS
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GENERAL OPTIMIZATION GUIDELINESPack
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GENERAL OPTIMIZATION GUIDELINES3.5.
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GENERAL OPTIMIZATION GUIDELINESFor
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GENERAL OPTIMIZATION GUIDELINESAs a
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GENERAL OPTIMIZATION GUIDELINESTher
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GENERAL OPTIMIZATION GUIDELINES—
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GENERAL OPTIMIZATION GUIDELINESmore
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GENERAL OPTIMIZATION GUIDELINESrequ
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GENERAL OPTIMIZATION GUIDELINESmiss
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GENERAL OPTIMIZATION GUIDELINESpref
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GENERAL OPTIMIZATION GUIDELINESpref
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GENERAL OPTIMIZATION GUIDELINES—
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GENERAL OPTIMIZATION GUIDELINESTher
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GENERAL OPTIMIZATION GUIDELINESstat
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GENERAL OPTIMIZATION GUIDELINESexte
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GENERAL OPTIMIZATION GUIDELINESFor
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CODING FOR SIMD ARCHITECTURES4.1.1
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CODING FOR SIMD ARCHITECTURESSoftwa
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CODING FOR SIMD ARCHITECTURESTo use
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CODING FOR SIMD ARCHITECTURESExampl
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CODING FOR SIMD ARCHITECTURESmance
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CODING FOR SIMD ARCHITECTURESpurpos
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CODING FOR SIMD ARCHITECTURESIf the
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CODING FOR SIMD ARCHITECTURESExampl
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CODING FOR SIMD ARCHITECTURES• Us
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CODING FOR SIMD ARCHITECTURESpatter
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CODING FOR SIMD ARCHITECTURESmoves
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CODING FOR SIMD ARCHITECTURES4-28
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OPTIMIZING FOR SIMD INTEGER APPLICA
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OPTIMIZING FOR SIMD FLOATING-POINT
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MULTICORE AND HYPER-THREADING TECHN
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OPTIMIZING CACHE USAGE• Take adva
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OPTIMIZING CACHE USAGEHardware pref
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OPTIMIZING CACHE USAGEThe non-tempo
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OPTIMIZING CACHE USAGE9.5.1.3 Memor
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OPTIMIZING CACHE USAGENOTEFailure t
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OPTIMIZING CACHE USAGE9.5.5 CLFLUSH
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OPTIMIZING CACHE USAGE• The hardw
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OPTIMIZING CACHE USAGETimeExecution
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OPTIMIZING CACHE USAGEschedule pref
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OPTIMIZING CACHE USAGEtime is large
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OPTIMIZING CACHE USAGEresource stal
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OPTIMIZING CACHE USAGEPrefetchntaDa
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OPTIMIZING CACHE USAGEExample 9-7.
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OPTIMIZING CACHE USAGEA characteris
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OPTIMIZING CACHE USAGE9.7 MEMORY OP
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OPTIMIZING CACHE USAGE9.7.2.3 Concl
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OPTIMIZING CACHE USAGEis not reside
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OPTIMIZING CACHE USAGEExample 9-11.
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OPTIMIZING CACHE USAGETable 9-3. De
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OPTIMIZING CACHE USAGE• If a proc
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64-BIT MODE CODING GUIDELINESAssemb
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64-BIT MODE CODING GUIDELINESinstru
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64-BIT MODE CODING GUIDELINES9-6
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POWER OPTIMIZATION FOR MOBILE USAGE
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APPLICATION PERFORMANCE TOOLSThe /f
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INSTRUCTION LATENCY AND THROUGHPUT
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INSTRUCTION LATENCY AND THROUGHPUTC
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STACK ALIGNMENTThe solution to this
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STACK ALIGNMENTExample D-1. Aligned
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STACK ALIGNMENTExample D-2. Aligned
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STACK ALIGNMENTD-8
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SUMMARY OF RULES AND SUGGESTIONSret
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SUMMARY OF RULES AND SUGGESTIONSfou
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SUMMARY OF RULES AND SUGGESTIONSvar
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SUMMARY OF RULES AND SUGGESTIONSto
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SUMMARY OF RULES AND SUGGESTIONSCor
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SUMMARY OF RULES AND SUGGESTIONSE-1
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INDEXsummary of rules, E-1tuning hi
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INDEXevent ratios, B-50execution co
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INDEXprefetching, 8-5SFENCE instruc
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INDEXPMAXSW, 5-28PMAXUB, 5-28PMINSW
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INDEXIndex-10
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