Intel® 64 and IA-32 Architectures Optimization Reference Manual

USING PERFORMANCE MONITORING EVENTS35. Loads Blocked by Unknown Store Data Rate: LOAD_BLOCK.STD /CPU_CLK_UNHALTED.COREA high value for “Loads Blocked by Unknown Store Data Rate” indicates that loadsare frequently blocked by preceding stores with unknown data and implies performancepenalty.B.7.5.4Memory DisambiguationThe memory disambiguation feature of Intel Core microarchitecture eliminates mostof the non-required load blocks by stores with unknown address. When this featurefails (possibly due to flaky load - store disambiguation cases) the eventLOAD_BLOCK.STA will be counted and also MEMORY_DISAMBIGUATION.RESET.B.7.5.5Load Operation Address Translation36. L0 DTLB Miss due to Loads - Performance Impact: DTLB_MISSES.L0_MISS_LD *2 / CPU_CLK_UNHALTED.COREHigh number of DTLB0 misses indicates that the data set that the workload usesspans a number of pages that is bigger than the DTLB0. The high number of missesis expected to impact workload performance only if the CPI (Ratio 1) is low - around0.8. Otherwise, it is likely that the DTLB0 miss cycles are hidden by other latencies.B.7.6Memory Sub-System - Cache Misses RatiosB.7.6.1Locating Cache Misses in the CodeIntel Core microarchitecture provides you with precise events for retired load instructionsthat miss the L1 data cache or the L2 cache. As precise events they provide theinstruction pointer of the instruction following the one that caused the event. Thereforethe instruction that comes immediately prior to the pointed instruction is the onethat causes the cache miss. These events are most helpful to quickly identify onwhich loads to focus to fix a performance problem. The events are:MEM_LOAD_RETIRE.L1D_MISSMEM_LOAD_RETIRE.L1D_LINE_MISSMEM_LOAD_RETIRE.L2_MISSMEM_LOAD_RETIRE.L2_LINE_MISSB-57