Intel® 64 and IA-32 Architectures Optimization Reference Manual

CONTENTSFigure 9-7. Cache Blocking – Temporally Adjacent and Non-adjacent Passes . . . . . . . . . . . . . . .8-23Figure 9-8. Examples of Prefetch and Strip-mining for Temporally Adjacent andNon-Adjacent Passes Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-24Figure 9-9. Single-Pass Vs. Multi-Pass 3D Geometry Engines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-29Figure 10-1. Performance History and State Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-2Figure 10-2. Active Time Versus Halted Time of a Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-3Figure 10-3. Application of C-states to Idle Time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-4Figure 10-4. Profiles of Coarse Task Scheduling and Power Consumption . . . . . . . . . . . . . . . . . . .10-9Figure 10-5. Thread Migration in a Multicore Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-12Figure 10-6. Progression to Deeper Sleep . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-13Figure A-1. Intel Thread Profiler Showing Critical Paths of Threaded Execution Timelines. . .A-15Figure B-1. Relationships Between Cache Hierarchy, IOQ, BSQ and FSB . . . . . . . . . . . . . . . . . . . .B-31Figure B-2. Performance Events Drill-Down and Software Tuning Feedback Loop . . . . . . . . . .B-46Figure 4-1. Stack Frames Based on Alignment Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-2PAGExix