Intel® 64 and IA-32 Architectures Optimization Reference Manual

POWER OPTIMIZATION FOR MOBILE USAGESWhen the lowest possible operating point (highest P-state) is reached, there is noneed for dividing computations. Instead, use longer idle periods to allow theprocessor to enter a deeper low power mode.10.4.6 Enabling Intel ® Enhanced Deeper SleepIn typical mobile computing usages, the processor is idle most of the time.Conserving battery life must address reducing static power consumption.Typical OS power management policy periodically evaluates opportunities to reducestatic power consumption by moving to lower-power C-states. Generally, the longera processor stays idle, OS power management policy directs the processor intodeeper low-power C-states.After an application reaches the lowest possible P-state, it should consolidate computationsin larger chunks to enable the processor to enter deeper C-States betweencomputations. This technique utilizes the fact that the decision to change frequencyis made based on a larger window of time than the period to decide to enter deepsleep. If the processor is to enter a processor-specific C4 state to take advantage ofaggressive static power reduction features, the decision should be based on:• Whether the QOS can be maintained in spite of the fact that the processor will bein a low-power, long-exit-latency state for a long period.• Whether the interval in which the processor stays in C4 is long enough toamortize the longer exit latency of this low-power C state.Eventually, if the interval is large enough, the processor will be able to enter deepersleep and save a considerable amount of power. The following guidelines can helpapplications take advantage of Intel ® Enhanced Deeper Sleep:• Avoid setting higher interrupt rates. Shorter periods between interrupts maykeep OSes from entering lower power states. This is because transition to/from adeep C-state consumes power, in addition to a latency penalty. In some cases,the overhead may outweigh power savings.• Avoid polling hardware. In a ACPI C3 type state, the processor may stopsnooping and each bus activity (including DMA and bus mastering) requiresmoving the processor to a lower-numbered C-state type. The lower-numberedstate type is usually C2, but may even be C0. The situation is significantlyimproved in the Intel Core Solo processor (compared to previous generations ofthe Pentium M processors), but polling will likely prevent the processor fromentering into highest-numbered, processor-specific C-state.10.4.7 Multicore ConsiderationsMulticore processors deserves some special considerations when planning powersavings. The dual-core architecture in Intel Core Duo processor and mobile processorsbased on Intel Core microarchitecture provide additional potential for powersavings for multi-threaded applications.10-10