Intel® 64 and IA-32 Architectures Optimization Reference Manual

APPENDIX BUSING PERFORMANCE MONITORING EVENTSPerformance monitoring events provide facilities to characterize the interactionbetween programmed sequences of instructions and microarchitectural subsystems.Performance monitoring events are described in Chapter 18 and AppendixA of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B.The first part of this chapter provides information on how to use performance eventsspecific to processors based on the Intel NetBurst microarchitecture. Section B.5discusses similar topics for performance events available on Intel Core Solo and IntelCore Duo processors.B.1 PENTIUM ® 4 PROCESSOR PERFORMANCE METRICSThe descriptions of Intel Pentium 4 processor performance metrics use terminologythat is specific to the Intel NetBurst microarchitecture and to implementations in thePentium 4 and Intel Xeon processors. The performance metrics in Table B-1 throughTable B-13 apply to processors with a CPUID signature that matches family encoding15, mode encoding 0, 1, 2, 3, 4, or 6. Several new performance metrics are availableto IA-32 processors with a CPUID signature that matches family encoding 15, modeencoding 3; the new metrics are listed in Table B-11.The performance metrics listed in Tables B-1 through B-7 may be applicable toprocessors that support HT Technology. See Appendix B.4, “Using PerformanceMetrics with Hyper-Threading Technology.”B.1.1Pentium ® 4 Processor-Specific TerminologyB.1.1.1Bogus, Non-bogus, RetireBranch mispredictions incur a large penalty on microprocessors with deep pipelines.In general, the direction of branches can be predicted with a high degree of accuracyby the front end of the Intel Pentium 4 processor, such that most computations canbe performed along the predicted path while waiting for the resolution of the branch.In the event of a misprediction, instructions and μops that were scheduled to executealong the mispredicted path must be cancelled. These instructions and μops arereferred to as bogus instructions and bogus μops. A number of Pentium 4 processorperformance monitoring events, for example, instruction_ retired and μops_retired,can count instructions or mops that are retired based on the characterization ofbogus versus non-bogus.Vol. 1 B-1