Intel® 64 and IA-32 Architectures Optimization Reference Manual

GENERAL OPTIMIZATION GUIDELINES— On Pentium 4 and Intel Xeon processors with a CPUID signature of familyencoding 15, model encoding 3; the data conflict condition applies toaddresses having identical values in bits 21:6.3.6.7.3 Aliasing Cases in the Pentium M, Intel Core Solo, Intel Core Duoand Intel Core 2 Duo ProcessorsPentium M, Intel Core Solo, Intel Core Duo and Intel Core 2 Duo processors have thefollowing aliasing case:• Store forwarding — If a store to an address is followed by a load from the sameaddress, the load will not proceed until the store data is available. If a store isfollowed by a load and their addresses differ by a multiple of 4 KBytes, the loadstalls until the store operation completes.Assembly/Compiler Coding Rule 55. (H impact, M generality) Avoid having astore followed by a non-dependent load with addresses that differ by a multiple of4 KBytes. Also, lay out data or order computation to avoid having cache lines thathave linear addresses that are a multiple of 64 KBytes apart in the same workingset. Avoid having more than 4 cache lines that are some multiple of 2 KBytes apartin the same first-level cache working set, and avoid having more than 8 cache linesthat are some multiple of 4 KBytes apart in the same first-level cache working set.When declaring multiple arrays that are referenced with the same index and are eacha multiple of 64 KBytes (as can happen with STRUCT_OF_ARRAY data layouts), padthem to avoid declaring them contiguously. Padding can be accomplished by eitherintervening declarations of other variables or by artificially increasing the dimension.User/Source Coding Rule 8. (H impact, ML generality) Consider using aspecial memory allocation library with address offset capability to avoid aliasing.One way to implement a memory allocator to avoid aliasing is to allocate more thanenough space and pad. For example, allocate structures that are 68 KB instead of64 KBytes to avoid the 64-KByte aliasing, or have the allocator pad and returnrandom offsets that are a multiple of 128 Bytes (the size of a cache line).User/Source Coding Rule 9. (M impact, M generality) When padding variabledeclarations to avoid aliasing, the greatest benefit comes from avoiding aliasing onsecond-level cache lines, suggesting an offset of 128 bytes or more.4-KByte memory aliasing occurs when the code accesses two different memory locationswith a 4-KByte offset between them. The 4-KByte aliasing situation can manifestin a memory copy routine where the addresses of the source buffer anddestination buffer maintain a constant offset and the constant offset happens to be amultiple of the byte increment from one iteration to the next.Example 3-38 shows a routine that copies 16 bytes of memory in each iteration of aloop. If the offsets (modular 4096) between source buffer (EAX) and destinationbuffer (EDX) differ by 16, 32, 48, 64, 80; loads have to wait until stores have beenretired before they can continue. For example at offset 16, the load of the next iterationis 4-KByte aliased current iteration store, therefore the loop must wait until thestore operation completes, making the entire loop serialized. The amount of time3-62