Intel® 64 and IA-32 Architectures Optimization Reference Manual

INTEL® 64 AND IA-32 PROCESSOR ARCHITECTURES• Intel ® Advanced Digital Media Boost improves most 128-bit SIMD instructionswith single-cycle throughput and floating-point operations. Featuresinclude:— Single-cycle throughput of most 128-bit SIMD instructions— Up to eight floating-point operations per cycle— Three issue ports available to dispatching SIMD instructions for execution2.1.1 Intel ® Core Microarchitecture Pipeline OverviewThe pipeline of the Intel Core microarchitecture contains:• An in-order issue front end that fetches instruction streams from memory, withfour instruction decoders to supply decoded instruction (μops) to the out-oforderexecution core.• An out-of-order superscalar execution core that can issue up to six μops per cycle(see Table 2-2) and reorder μops to execute as soon as sources are ready andexecution resources are available.• An in-order retirement unit that ensures the results of execution of μops areprocessed and architectural states are updated according to the original programorder.Intel Core 2 Extreme processor X6800, Intel Core 2 Duo processors and Intel Xeonprocessor 3000, 5100 series implement two processor cores based on the Intel Coremicroarchitecture. Intel Core 2 Extreme quad-core processor, Intel Core 2 Quadprocessors and Intel Xeon processor 3200 series, 5300 series implement fourprocessor cores. Each physical package of these quad-core processors contains twoprocessor dies, each die containing two processor cores. The functionality of thesubsystems in each core are depicted in Figure 2-1.2-3