IntelÂ® 64 and IA-32 Architectures Optimization Reference Manual

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APPLICATION PERFORMANCE TOOLSThe /fast option maximizes speed across the entire program. For most Intel 64 andIA-32 processors, the “/fast” option is equivalent to “/O3 /Qipo /QxP” (-Q3 -ipo -static -xP on Linux). For Mac OS, the "-fast" option is equivalent to "-O3 -ipo".All the command-line options are described in Intel ® C++ Compiler documentation.A.1.1Recommended Optimization Settings for Intel 64 and IA-32Processors64-bit addressable code can only run in 64-bit mode of processors that supportIntel 64 architecture. The optimal compiler settings for 64-bit code generation isdifferent from 32-bit code generation. Table A-1 lists recommended compiler optionsfor generating 32-bit code for Intel 64 and IA-32 processors. Table A-1 also appliesto code targeted to run in compatibility mode on an Intel 64 processor, but does notapply to running in 64-bit mode. Table A-2 lists recommended compiler options forgenerating 64-bit code for Intel 64 processors, it only applies to code target to run in64-bit mode. Intel compilers provide separate compiler binary to generate 64-bitcode versus 32-bit code. The 64-bit compiler binary generates only 64-bit addressablecode.Table A-1. Recommended IA-32 Processor Optimization OptionsNeed Recommendation Comments• /QxT (-xT onLinux)Best performanceon Intel Core 2processor family andIntel Xeon processor3000 and 5100series, utilizingSSSE3 and otherprocessor-specificinstructionsBest performanceon Intel Core 2processor family andIntel Xeon processor3000 and 5100series, utilizingSSSE3; runs on non-Intel processorsupporting SSE2Best performanceon IA-32 processorswith SSE3instruction support• /QaxT /QxW (-axT-xW on Linux)• Single code path• Will not run on earlier processors thatdo not support SSSE3• Multiple code path are generated• Be sure to validate your application onall systems where it may be deployed./QxP (-xP on Linux) • Single code path• Will not run on earlier processors.thatdo not support SSE3A-2
APPLICATION PERFORMANCE TOOLSBest performanceon IA-32 processorswith SSE2instruction supportBest performanceon IA-32 processorswith SSE3instruction supportfor multiple codepathsTable A-1. Recommended IA-32 Processor Optimization OptionsNeed Recommendation Comments/QaxN (-axN on Linux)Optimized for Pentium4 and Pentium Mprocessors, and anoptimized, generic codepathto run on otherprocessors• /QaxP /QxW (-axP-xW on Linux)• Optimized forPentium 4processor andPentium 4processor withSSE3 instructionsupport• Multiple code paths are generated.• Use /QxN (-xN for Linux) if you knowyour application will not be run onprocessors older than the Pentium 4 orPentium M processors.Generates two code paths:• one for the Pentium 4 processor• one for the Pentium 4 processor ornon-Intel processors with SSE3instruction support.Table A-2. Recommended Processor Optimization Options for 64-bit CodeNeed Recommendation Comments• /QxT (-xT onLinux)Best performance on Intel Core2 processor family and IntelXeon processor 3000 and5100 series, utilizing SSSE3and other processor-specificinstructionsBest performance on Intel Core2 processor family and IntelXeon processor 3000 and5100 series, utilizing SSSE3;runs on non-Intel processorsupporting SSE2Best performance on otherprocessors supporting Intel 64architecture, utilizing SSE3where possible• /QaxT /QxW (-axT-xW on Linux)• /QxP (-xP onLinux)• Single code path• Will not run on earlierprocessors that do notsupport SSSE3• Multiple code path aregenerated• Be sure to validate yourapplication on all systemswhere it may be deployed.• Single code path aregenerated• Will not run on processorsthat do not support Intel 64architecture and SSE3.A-3
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NIntel® 64 and IA-32 Architectures
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CONTENTS2.3.1 Front End. . . . . .
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CONTENTS3.7 PREFETCHING . . . . . .
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CONTENTS5.7.2.1 Increasing Memory B
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CONTENTS9.5.3 Streaming Store Instr
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CONTENTSB.7.4.3B.7.4.4B.7.4.5B.7.4.
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CONTENTSExample 4-1. Identification
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CONTENTSExample 9-8. Using HW Prefe
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CONTENTSFigure 9-7. Cache Blocking
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CHAPTER 1INTRODUCTIONThe Intel® 64
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INTRODUCTION• Chapter 10: Power O
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CHAPTER 2INTEL ® 64 AND IA-32 PROC
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INTEL® 64 AND IA-32 PROCESSOR ARCH
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CHAPTER 3GENERAL OPTIMIZATION GUIDE
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GENERAL OPTIMIZATION GUIDELINESThe
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GENERAL OPTIMIZATION GUIDELINEScomp
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GENERAL OPTIMIZATION GUIDELINES•
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GENERAL OPTIMIZATION GUIDELINESExam
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GENERAL OPTIMIZATION GUIDELINESthro
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GENERAL OPTIMIZATION GUIDELINESAsse
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GENERAL OPTIMIZATION GUIDELINESpred
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GENERAL OPTIMIZATION GUIDELINESIn t
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GENERAL OPTIMIZATION GUIDELINESBeca
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GENERAL OPTIMIZATION GUIDELINESInst
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GENERAL OPTIMIZATION GUIDELINESXOR
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GENERAL OPTIMIZATION GUIDELINESUse
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GENERAL OPTIMIZATION GUIDELINESMOVS
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GENERAL OPTIMIZATION GUIDELINESPack
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GENERAL OPTIMIZATION GUIDELINES3.5.
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GENERAL OPTIMIZATION GUIDELINESFor
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GENERAL OPTIMIZATION GUIDELINESAs a
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GENERAL OPTIMIZATION GUIDELINESTher
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GENERAL OPTIMIZATION GUIDELINES—
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GENERAL OPTIMIZATION GUIDELINESmore
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GENERAL OPTIMIZATION GUIDELINESrequ
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GENERAL OPTIMIZATION GUIDELINESmiss
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GENERAL OPTIMIZATION GUIDELINESpref
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GENERAL OPTIMIZATION GUIDELINESpref
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GENERAL OPTIMIZATION GUIDELINES—
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GENERAL OPTIMIZATION GUIDELINESTher
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GENERAL OPTIMIZATION GUIDELINESstat
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GENERAL OPTIMIZATION GUIDELINESexte
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GENERAL OPTIMIZATION GUIDELINESFor
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CODING FOR SIMD ARCHITECTURES4.1.1
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CODING FOR SIMD ARCHITECTURESSoftwa
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CODING FOR SIMD ARCHITECTURESTo use
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CODING FOR SIMD ARCHITECTURESExampl
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CODING FOR SIMD ARCHITECTURESmance
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CODING FOR SIMD ARCHITECTURESpurpos
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CODING FOR SIMD ARCHITECTURESIf the
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CODING FOR SIMD ARCHITECTURESExampl
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CODING FOR SIMD ARCHITECTURES• Us
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CODING FOR SIMD ARCHITECTURESpatter
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CODING FOR SIMD ARCHITECTURESmoves
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CODING FOR SIMD ARCHITECTURES4-28
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OPTIMIZING FOR SIMD INTEGER APPLICA
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OPTIMIZING FOR SIMD FLOATING-POINT
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MULTICORE AND HYPER-THREADING TECHN
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OPTIMIZING CACHE USAGE• Take adva
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OPTIMIZING CACHE USAGEHardware pref
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OPTIMIZING CACHE USAGEThe non-tempo
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OPTIMIZING CACHE USAGE9.5.1.3 Memor
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OPTIMIZING CACHE USAGENOTEFailure t
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Page 334 and 335: 64-BIT MODE CODING GUIDELINESAssemb
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Page 340 and 341: POWER OPTIMIZATION FOR MOBILE USAGE
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Page 370 and 371: USING PERFORMANCE MONITORING EVENTS
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USING PERFORMANCE MONITORING EVENTS
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INSTRUCTION LATENCY AND THROUGHPUTW
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INSTRUCTION LATENCY AND THROUGHPUTo
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INSTRUCTION LATENCY AND THROUGHPUTT
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INSTRUCTION LATENCY AND THROUGHPUT
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INSTRUCTION LATENCY AND THROUGHPUTC
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STACK ALIGNMENTThe solution to this
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STACK ALIGNMENTExample D-1. Aligned
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STACK ALIGNMENTExample D-2. Aligned
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STACK ALIGNMENTD-8
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SUMMARY OF RULES AND SUGGESTIONSret
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SUMMARY OF RULES AND SUGGESTIONSfou
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SUMMARY OF RULES AND SUGGESTIONSvar
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SUMMARY OF RULES AND SUGGESTIONSto
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SUMMARY OF RULES AND SUGGESTIONSCor
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SUMMARY OF RULES AND SUGGESTIONSE-1
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INDEXsummary of rules, E-1tuning hi
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INDEXevent ratios, B-50execution co
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INDEXprefetching, 8-5SFENCE instruc
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INDEXPMAXSW, 5-28PMAXUB, 5-28PMINSW
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INDEXIndex-10
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IntelÂ® 64 and IA-32 Architectures Optimization Reference Manual

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