IntelÂ® 64 and IA-32 Architectures Optimization Reference Manual

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OPTIMIZING FOR SIMD INTEGER APPLICATIONSExample 5-21. Basic C Implementation of RGBA to BGRA Conversionvoid BGRA_RGBA_Convert(BGRA *source, RGBA *dest, int num_pixels){for(int i = 0; i < num_pixels; i++){dest[i].r = source[i].r;dest[i].g = source[i].g;dest[i].b = source[i].b;dest[i].a = source[i].a;}}Example 5-22 and Example 5-23 show SSE2 code and SSSE3 code for pixel formatconversion. In the SSSE3 example, PSHUFB replaces six SSE2 instructions.Example 5-22. Color Pixel Format Conversion Using SSE2; Optimized for SSE2mov esi, srcmov edi, destmov ecx, iterationsmovdqa xmm0, ag_mask //{0,ff,0,ff,0,ff,0,ff,0,ff,0,ff,0,ff,0,ff}movdqa xmm5, rb_mask //{ff,0,ff,0,ff,0,ff,0,ff,0,ff,0,ff,0,ff,0}mov eax, remainderconvert16Pixs: // 16 pixels, 64 byte per iterationmovdqa xmm1, [esi] // xmm1 = [r3g3b3a3,r2g2b2a2,r1g1b1a1,r0g0b0a0]movdqa xmm2, xmm1movdqa xmm7, xmm1 //xmm7 abgrpsrld xmm2, 16 //xmm2 00abpslld xmm1, 16 //xmm1 gr00por xmm1, xmm2 //xmm1 grabpand xmm7, xmm0 //xmm7 a0g0pand xmm1, xmm5 //xmm1 0r0bpor xmm1, xmm7 //xmm1 argbmovdqa [edi], xmm15-22
OPTIMIZING FOR SIMD INTEGER APPLICATIONSExample 5-22. Color Pixel Format Conversion Using SSE2 (Contd.)//repeats for another 3*16 bytes…add esi, 64add edi, 64sub ecx, 1jnz convert16PixsExample 5-23. Color Pixel Format Conversion Using SSSE3; Optimized for SSSE3mov esi, srcmov edi, destmov ecx, iterationsmovdqa xmm0, _shufb// xmm0 = [15,12,13,14,11,8,9,10,7,4,5,6,3,0,1,2]mov eax, remainderconvert16Pixs: // 16 pixels, 64 byte per iterationmovdqa xmm1, [esi]// xmm1 = [r3g3b3a3,r2g2b2a2,r1g1b1a1,r0g0b0a0]movdqa xmm2, [esi+16]pshufb xmm1, xmm0// xmm1 = [b3g3r3a3,b2g2r2a2,b1g1r1a1,b0g0r0a0]movdqa [edi], xmm1//repeats for another 3*16 bytes…add esi, 64add edi, 64sub ecx, 1jnz convert16Pixs5.6.5 Endian ConversionThe PSHUFB instruction can also be used to reverse byte ordering within a doubleword.It is more efficient than traditional techniques, such as BSWAP.5-23
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NIntel® 64 and IA-32 Architectures
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CONTENTS2.3.1 Front End. . . . . .
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CONTENTS3.7 PREFETCHING . . . . . .
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CONTENTS5.7.2.1 Increasing Memory B
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CONTENTS9.5.3 Streaming Store Instr
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CONTENTSB.7.4.3B.7.4.4B.7.4.5B.7.4.
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CONTENTSExample 4-1. Identification
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CONTENTSExample 9-8. Using HW Prefe
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CONTENTSFigure 9-7. Cache Blocking
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CHAPTER 1INTRODUCTIONThe Intel® 64
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INTRODUCTION• Chapter 10: Power O
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CHAPTER 2INTEL ® 64 AND IA-32 PROC
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INTEL® 64 AND IA-32 PROCESSOR ARCH
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CHAPTER 3GENERAL OPTIMIZATION GUIDE
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GENERAL OPTIMIZATION GUIDELINESThe
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GENERAL OPTIMIZATION GUIDELINEScomp
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GENERAL OPTIMIZATION GUIDELINES•
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GENERAL OPTIMIZATION GUIDELINESExam
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GENERAL OPTIMIZATION GUIDELINESthro
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GENERAL OPTIMIZATION GUIDELINESAsse
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GENERAL OPTIMIZATION GUIDELINESpred
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GENERAL OPTIMIZATION GUIDELINESBeca
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GENERAL OPTIMIZATION GUIDELINESInst
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GENERAL OPTIMIZATION GUIDELINESXOR
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GENERAL OPTIMIZATION GUIDELINESUse
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GENERAL OPTIMIZATION GUIDELINESMOVS
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GENERAL OPTIMIZATION GUIDELINESPack
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GENERAL OPTIMIZATION GUIDELINES3.5.
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GENERAL OPTIMIZATION GUIDELINESFor
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GENERAL OPTIMIZATION GUIDELINESAs a
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GENERAL OPTIMIZATION GUIDELINESTher
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GENERAL OPTIMIZATION GUIDELINES—
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GENERAL OPTIMIZATION GUIDELINESmore
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GENERAL OPTIMIZATION GUIDELINESrequ
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GENERAL OPTIMIZATION GUIDELINESmiss
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GENERAL OPTIMIZATION GUIDELINESpref
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GENERAL OPTIMIZATION GUIDELINESpref
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GENERAL OPTIMIZATION GUIDELINES—
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GENERAL OPTIMIZATION GUIDELINESTher
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GENERAL OPTIMIZATION GUIDELINESstat
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GENERAL OPTIMIZATION GUIDELINESexte
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Page 162 and 163: CODING FOR SIMD ARCHITECTURES4.1.1
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Page 172 and 173: CODING FOR SIMD ARCHITECTURESmance
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Page 182 and 183: CODING FOR SIMD ARCHITECTURES• Us
Page 184 and 185: CODING FOR SIMD ARCHITECTURESpatter
Page 186 and 187: CODING FOR SIMD ARCHITECTURESmoves
Page 188 and 189: CODING FOR SIMD ARCHITECTURES4-28
Page 190 and 191: OPTIMIZING FOR SIMD INTEGER APPLICA
Page 228 and 229: OPTIMIZING FOR SIMD FLOATING-POINT
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MULTICORE AND HYPER-THREADING TECHN
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OPTIMIZING CACHE USAGE• Take adva
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OPTIMIZING CACHE USAGEHardware pref
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OPTIMIZING CACHE USAGEThe non-tempo
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OPTIMIZING CACHE USAGE9.5.1.3 Memor
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OPTIMIZING CACHE USAGENOTEFailure t
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OPTIMIZING CACHE USAGE9.5.5 CLFLUSH
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OPTIMIZING CACHE USAGE• The hardw
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OPTIMIZING CACHE USAGETimeExecution
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OPTIMIZING CACHE USAGEschedule pref
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OPTIMIZING CACHE USAGEtime is large
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OPTIMIZING CACHE USAGEresource stal
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OPTIMIZING CACHE USAGEPrefetchntaDa
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OPTIMIZING CACHE USAGEExample 9-7.
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OPTIMIZING CACHE USAGEA characteris
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OPTIMIZING CACHE USAGE9.7 MEMORY OP
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OPTIMIZING CACHE USAGE9.7.2.3 Concl
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OPTIMIZING CACHE USAGEis not reside
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OPTIMIZING CACHE USAGEExample 9-11.
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OPTIMIZING CACHE USAGETable 9-3. De
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OPTIMIZING CACHE USAGE• If a proc
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64-BIT MODE CODING GUIDELINESAssemb
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64-BIT MODE CODING GUIDELINESinstru
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64-BIT MODE CODING GUIDELINES9-6
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POWER OPTIMIZATION FOR MOBILE USAGE
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APPLICATION PERFORMANCE TOOLSThe /f
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APPLICATION PERFORMANCE TOOLSTable
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APPLICATION PERFORMANCE TOOLSA.1.6.
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APPLICATION PERFORMANCE TOOLSExampl
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APPLICATION PERFORMANCE TOOLSExampl
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APPLICATION PERFORMANCE TOOLSprogra
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APPLICATION PERFORMANCE TOOLSThe Li
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APPLICATION PERFORMANCE TOOLSA.5 IN
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USING PERFORMANCE MONITORING EVENTS
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INSTRUCTION LATENCY AND THROUGHPUTW
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INSTRUCTION LATENCY AND THROUGHPUTo
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INSTRUCTION LATENCY AND THROUGHPUTT
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INSTRUCTION LATENCY AND THROUGHPUT
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INSTRUCTION LATENCY AND THROUGHPUTC
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STACK ALIGNMENTThe solution to this
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STACK ALIGNMENTExample D-1. Aligned
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STACK ALIGNMENTExample D-2. Aligned
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STACK ALIGNMENTD-8
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SUMMARY OF RULES AND SUGGESTIONSret
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SUMMARY OF RULES AND SUGGESTIONSfou
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SUMMARY OF RULES AND SUGGESTIONSvar
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SUMMARY OF RULES AND SUGGESTIONSCor
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SUMMARY OF RULES AND SUGGESTIONSE-1
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INDEXsummary of rules, E-1tuning hi
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INDEXevent ratios, B-50execution co
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INDEXprefetching, 8-5SFENCE instruc
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INDEXPMAXSW, 5-28PMAXUB, 5-28PMINSW
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INDEXIndex-10
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IntelÂ® 64 and IA-32 Architectures Optimization Reference Manual

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