Plenarvorträge - DPG-Tagungen

Halbleiterphysik Montag
concentration, which was confirmed by SIMS measurements, neither segregation
nor coulombic repulsion plays an important role in the system
HL 10 Baulemente
discussed here.
This work was supported by the DFG, SFB 602 TP A7.
Zeit: Montag 15:15–16:30 Raum: H13
HL 10.1 Mo 15:15 H13
Efficiency of High-Brightness AlGaInP LEDs: Model and Experiment
— •P. Altieri, A. Jaeger, R. Windisch, N. Linder, P.
Stauss, R. Oberschmid, and K. Streubel — OSRAM Opto Semiconductors
GmbH, Wernerwerkstr. 2, 93049 Regensburg
We present a quantitative analysis of the internal quantum efficiency
of high-brightness AlGaInP light-emitting devices (LEDs) with an emission
wavelength ranging from 650 nm to 560 nm. The wavelength is
adjusted by varying the Aluminum content in the active region. The
evaluation is based on measurements of the external quantum efficiency
of the LEDs as a function of the operating current (0.1-20 mA) and
temperature (298-360 K). The determination of the internal quantum efficiency
is performed by means of a model that takes into account the
radiative and nonradiative recombination in the active layer, the diffusive
leakage of charge carriers into the confining InAlP layers and the influence
of photon recycling on the light extraction efficiency. In the current
range here analyzed red emitting LEDs show maximum internal quantum
efficiencies close to 100 %. The maximum efficiency decreases with
decreasing wavelength down to about 7 % for green LEDs. This reduction
is mainly due to leakage which accounts for the loss of about 75 % of the
injected carriers. In addition, the nonradiative recombination increases
by approximately one order of magnitude from red to green LEDs.
HL 10.2 Mo 15:30 H13
The Source-Gated Thin-Film Transistor — •Thomas Lindner 1 ,
Gernot Paasch 1 , and Susanne Scheinert 2 — 1 IFW Dresden —
2 TU Ilmenau
In thin-film transistors as usual the channel is controlled by the gate
and the current saturates when the drain end of the channel becomes
depleted due to the drain voltage. For this operation the channel contacts
to source and drain must be ohmic. Recently, source-gated thin-film
transistors (SGT) made by undoped a-Si:H have been introduced 1 . In the
SGT there is no direct contact between source and the channel. This design
is essentially the same as that one of the top contact (TOC) organic
field-effect transistor (FET) 2,3 . In the SGT in addition the source contact
is chosen as a depletion (Schottky) contact. In Refs.(2,3) the TOC
FET has been investigated also for Schottky contacts. In contrast to the
advantages of the SGT proposed in Ref.(1) we found that apart from
the unusual voltage dependencies of the current, the main feature of the
Schottky-contacted TOC FET is a strongly reduced current due to the
series resistance between source and the channel. Here a detailed simulation
study for the a-Si:H based SGT is presented revealing the operation
mode of this device.
1 J.M. Shannon, E.G. Gerstner, IEEE ED Letters 24 (2003) 405.
2 S. Scheinert, G. Paasch, T. Lindner, Synth. Met. 137 (2003) 1451.
3 T. Lindner, G. Paasch, S. Scheinert, J. Mat. Res., submitted.
HL 10.3 Mo 15:45 H13
Patterning of sub 50 nm structures for diffusion investigations
in vertical Double-Gate MOSFETs — •Jürgen Moers 1 , Stefan
Trellenkamp 1 , Susan Kluth 2 , Patrick Kluth 2 , David Alvarez
3,4 , Johannes Kretz 4 , Siegfried Mantl 1 , and Hans Lüth 1
— 1 Institute of Thin Films and Interfaces, Forschungszentrum Jülich, D-
52425 Jülich — 2 Australien National University, Canberra, ACT 0200,
Australia — 3 IMEC, Kapeldreef 75, B-3001 Leuven, Belgium — 4 Infineon
Technologies AG, D-81730 Munich
The tremendous increase in computational efficiency was made possible
by shrinking the dimension of microelectronic devices. This downsizing
led to the well known Short Channel Effects (SCE). To account for these
SCE the lateral layout was improved. For future CMOS applications this
will be not sufficient, therefore new architectures must be investigated.
One architecture is the Double-Gate-MOSFET, where the channel forming
thin silicon layer is sandwiched between two gates; these two gates
control the electric field in the silicon very efficiently and hence reduce
SCE. Heart of this device is a silicon ridge of ∼20 nm width, in which
the dopants are implanted. The channel length of the device is defined
by the implantation energy and the diffusion during the subsequent thermal
treatment. Therefore it is essential to investigate the diffusion in
nanostructures.
Sub 50 nm structures in silicon were prepared using electron beam
lithography and high selective reactive ion etching. First results show a
different boron diffusion due to reduced transient enhanced diffusion. A
qualitative interpretation of the effects are given.
HL 10.4 Mo 16:00 H13
Electrical characterization of temporary devices fabricated
with a double-tip AFM on semiconductive surfaces — •A.-D.
Müller 1 , F. Müller 1 , T.D. Long 1 , L.Q.T. Dung 1 , J. Mehner 2 ,
and M. Hietschold 1 — 1 Chemnitz University of Technology, Institute
of Physics, Solid Surface Analysis Group, 09107 Chemnitz — 2 Chemnitz
University of Technology, Institute of Electrical Engineering and
Information Technology, 09107 Chemnitz
Using a multiple cantilever device, semiconductor devices can be created
temporarily on a semiconductor`s surface to perform an electrical
measurement. The obtained electrical characteristics of such devices represent
the local electrical surface properties at the moment of the measurement.
This contribution presents the application of a double cantilever, which
has two tips with a lateral distance of 10 µm. Each tip has its own vertical
actuator, so that they can be placed on the surface independently of
each other with a detectable contact force in an Atomic Force Microscope
set-up. The observed electrical characteristics are compared with circuit
simulations using a MESFET model instead of the temporary device. On
silicon (111) with a natural oxide layer, for instance, a high surface conductivity
and a high barrier at the temporarily formed Pt/Si-interfaces
have been found.
HL 10.5 Mo 16:15 H13
Simulation and fabrication of complementary tunneling transistors
in silicon — •Peng-Fei Wang, Thomas Nirschl, Marcus
Weis, Doris Schmitt-Landsiedel, and Walter Hansch — Institute
for Technical Electronics, Technical University Munich, Arcisstr. 21,
80333 Munich, Germany
In this paper, a surface-tunneling transistor called TFET is fabricated
using the CMOS compatible technologies. The gate controlled band-toband
tunneling is realized in this transistor. The gate controlled surface
Esaki tunneling current is also observed at room temperature. Due to the
distinct working principle of this novel transistor, the low sub-threshold
leakage current and perfect drain current saturation can be obtained.
Compared to the conventional NMOS, the lower leakage current and
smaller Vth roll-off can be achieved. Since the impact ionization in this
transistor is caused by the electrons injected from tunneling junction,
TFET is also a hot electron transistor where the impact ionization can
be controlled by the gate voltage. In addition, the complementary TEFT
are fabricated on the same silicon substrate. The performances of the
n-channel TFET and the p-channel TFET will be discussed in detail.