ITT - Index of

I mm
__. ..L..L. _____ .......... __
SEMICONDUCTORS
J-K MASTER-SLAVE FLIP-FLOPS
These J-K flip-flops are based on the master-slave
principle and each has AND gate inputs for entry
into the master section which are controlled by the
clock pulse. The clock pulse also regulates the state
of the coupling transistors which connect the master
and slave sections. The sequence of operation
is as follows:
1. Isolate slave from master
2. Enter information from AN D gate inputs
to master
3. Disabi'e AN D gate inputs
4. Transfer information from master to
slave.
ITT5472, ITT7472
J_-_K_M_A_S_T_E_R_-S_L_A_V_E_F_L_I P_-F_L_O_P_S
DUAL- IN- LINE PACKAGE
PIN CONFIGURATION
(TOP VIEW)
HIGH
LOW
CLOCK WAVEFORM
KI CD
. FLAT PACKAGE
PIN CONFIGURATION
(TOP VIEW)
@K3
Notes:
J
TRUTH TABLE
tn
K
tn+1
°
0 0 On
0 1 0
1 0 1
1 1
°li
1. j = J 1 • J2 • J3
2. K = K 1 • K2 • K3.
3. tn = Bit time before clock pulse.
4; t n+ 1 = Bit time after clock pulse.
5. NC = No Internal Connection.
CLOCKeD
PRESET 0 .... +H+-'
vcc0
CLEAR 0 ... I-+++-...,
NCG)
JIG)
POSITIVE LOGIC:
....-----1"- @) K2
@Q
@GND
@o
'-----1-0 0 J3
0 J2
LOW INPUT TO PRESET SETS Q TO LOGICAL I
LOW INPUT TO CLEAR SETS Q TO LOGICAL 0
PRESET OR CLEAR ARE INDEPENDENT OF
CLOCK
recommended operating conditions Min Nom Max Unit
Supply Voltage V CC: ITT5472 Circuits ................................................................................. 4.5 5 5.5 V
ITT7472 Circuits ...................................................................................................................... 4.75 5 5.25 V
Operating Free-Air Temperature Range. T A: ITT5472 Circuits ....................................... -55 25 125 °c
ITT7472 Circuits .......................................:.............................;................................................ 0 25 70 °c
Normalized Fan-Out From Each Output. N ................................................:......................... 10
Width of Clock Pulse. tp(clock) (See figure 69) :...........................;.................................:... 20
Width of Preset Pulse. tp(presetl (See figure 70) ................................................................ 25
Width of Clear Pulse. tp(cleilr) (See figure 70) .................................................................;..· 25
Input Setup Time. tsetup (See figure 69) ............................................................................. ~tp(clock)
Input Hold Time. t hold ............................................................................................................. 0
ns
ns
ns
3-93