ITT - Index of

GENERAL INFORMATION ITT54H/74H SERIES TTL FAMILY
Fig. 2. Simplified analogy of TTL gate.
•
c
D
J
~Rc
{RL
R, ~
vn
\.!:!
VT1
r.:
\.!:!
R.
ra. VTZ \.!:!
T
+5V
When all the inputs are positive a logic '1' current
flows from the positive supply through Rg into the
base of VT1 which heavily conducts and turns VT2
'ON' into the saturated state. Since both VT1 and
VT2 are' saturated, there is insufficient voltage
across the base emitter terminals of VT3 to render
it conducting. The output voltage is about +0.2 V,
(i.e. saturation voltage of VT2). The collector current
of VT2 will consist of the total 'sinking' current
from the gates connected to the output terminal.
When the base current drive to VT2 is high, VT2
can remain saturated even with a large collector
current. with adverse circuit tolerances and temperature
variations. This permits a fan-out of up to
10. With a multiemitter transistor, more current
flows from a positive held input than with a conventional
D.T. L. gate (the leakage current of the reverse
biassed input diode) since the MET is biassed
in the inverted mode and the functions of emitter
and collector are reversed. However, the MET is designed
to have a very low inverse gain and IR is
kept to a minimum. IR will equal the emitter base
leakage current plus the product of inverse current
gain and IG.
2, LOW OR OFF STATE
The opposite state shown in Fig. 1 B is achieved
if the voltage of any number of inputs is reduced
below a threshold level of about + 1.5 volts. Fig.
1 B shows the conditions when input A is at +0.2
volts (a typical output voltage of a previous gate).
No base current flows into VT 1 since the collector
Q
, i
I
of the METis at too Iowa potential, with respect
to its base.
Therefore, no current will flow through VT1 and
VT2 other than leakage current (which can be
neglected in this analysis). The transistor VT3 will
conduct to provide sufficient output current to
maintain following gates connected to the output
terminal at 3.3 V positive in logic 1. The fan-out
is high (10) under worst case conditions because
of the low output impedance of VT3.
3, CHANGEOVER BETWEEN STATES
The transistor action of the MET considerably improves
the switching speed when compared with
a DTL gate. In switching from the ON to the OFF
state the MET saturates and rapidly removes the
charge stored in VT1 turning it off. Then VT2 begins
to turn off and VT3 turns on as the collector potential
of VT1 rises. VT3 assists VT2 to turn off and
pulls the output terminal rapidly positive, charging
any load capacitance. The diode D1 helps to prevent
VT2 and VT1 from conducting simultaneously
and RL limits the current through VT3 to a safe
value during the switch over if the output terminal
is accidentally shorted.
Fig. 3. Propagation delay waveforms.
r------V'H
vo~~:~~ =i-------\-----t~~ v"
I
I
"Bns;
I I
I 1
,-10 ns...,
OUTPUT ~I I,r--VOH
VOLTAGE _~_ - ----1-- -'- ___
-I 1 I +HV
VOl - ,-T I
I I I
1 1 I I
I I: I I
--l ',d-. f-- I 'pd+ I
I I I I
Switching from the OFF to the ON state is more
rapid than ON to OFF since none of the transistors
VT1, VT2 and MET are saturated ,in the OFF con-
, dition. The switch to the ON condition is particularly
fast owing to additional drive by transistor VT1 in
turning on VT2. Fig. 3 shows the typical switching
times from this gate.
3-14d