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APPLICATION DATA FOR OPEN COLLECTOR DEVICES<br />

Combined Fan-Out and Wire-OR Capabilities<br />

The open-collector TTL gate. when supplied with<br />

a proper load resistor (R). may be paralleled with<br />

other similar TTL gates to perform the wire-OR<br />

function. and simultaneously. w.ill drive from one to<br />

nine TTL loads. When no other open-collector gates<br />

are paralleled. this gate may be used to drive ten<br />

TTL loads. For any <strong>of</strong> these conditions an appropriate<br />

load resistor value must be determined for<br />

the desired circuit configuration. A maximu m<br />

resistor value must be determined which will<br />

ensure that sufficient load current (to TTL loads)<br />

and lout current (through paralleled outputs) will<br />

be available during a logical 1 level at the output.<br />

A minimum resistor value must be determined<br />

which will ensure that current through this resistor<br />

and sink current from the TTL loads will not cause<br />

the output voltage to rise above the logical 0 level<br />

even if one <strong>of</strong> the paralleled outputs is sinking all<br />

the current.<br />

in both conditions (logical 0 and logical 1) the value<br />

<strong>of</strong> RL is determined by:<br />

where: VR L is the voltage drop in<br />

volts. and IRL is the current in amperes.<br />

Logical 1 (<strong>of</strong>f level) Circuit Calculations (see<br />

figure A)<br />

The allowable voltage drop across the load resistor<br />

(VRL) is the difference between Vee applied and<br />

the Vout( 1) level required at the load:<br />

VRL = Vee -Vout(1) required<br />

The total current through the load resistor (I R L) is<br />

the sum <strong>of</strong> the load currents (lin( 1)) and <strong>of</strong>f-level<br />

reverse currents (lout( 1 )) through each <strong>of</strong> the wire­<br />

D R connected outputs:<br />

IRL = n olout(l) + N° lin(1) to TTL loads<br />

Therefore. calculations for the maximum value <strong>of</strong><br />

RL would be:<br />

R - Vee -Vout(1) required<br />

L(max) -<br />

n olout(l) + N olin(l)<br />

where: n = number <strong>of</strong> gates wire-OR<br />

connec!ed. and<br />

N = number <strong>of</strong> TTL loads.<br />

TTL LOADS<br />

Calculation:<br />

RL(max)<br />

Vee - Vout(1) required<br />

Tl o lout(1) + N o lin(1)<br />

~<br />

N = 3<br />

N° lin(1) = 3 o40I'A<br />

5-2.4 = ~ = 2321 n<br />

0.001 + 0.00012 0.00112<br />

Calculation<br />

'7 = 4<br />

Tl 0 lout(1) = 4 0 250 /JA<br />

R - Vee -Vout(l) required<br />

L(max) - no I + N 0 I<br />

out( 1) load<br />

FIGURE A -<br />

R _ 5 - 2.4<br />

L(max) - 0.001 + 0.00012<br />

LOGICAL 1 CIRCUIT CONDITIONS<br />

2.6 =2321Q<br />

0.00112<br />

3-12

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