ITT - Index of

GENERAL INFORMATION ITT54/74 SERIES TTL FAMILY
7. Similarly extemal inputs should be brought on
to the printed circuit con~ections at right angles
to the other wiring, the printed circuit itself being
laid out to ensure least coupling between
inputsand other ·connections.
8. If system speed is high, allowance should be
made when calculating power supply requirements
for the' increased network supply currents
due to current spiking and line driving .. An allowance
at 10 MHz of 15% for spiking and up
to 0.5 mA per each gate node for the line driving
wi" be adequate for this.
9. Decouple' every'1 0 gates or their equivalent in
MSI functions with 0.01 uF to 0.1 uF capacitors
of R. F. rating.
In conclusion, a careful perusal of the data sheet
together with the points mentioned above, will help
in achieving a trouble free logic design at the first
attempt.
DRIVING DTllOGIC FROM TTL DEVICES
When driving ITT930 series DTL from 74/5400 series
TTL the full fan-out of the TTL is available
. DRIVING TTl L.OGIC FROM DTl DEVICES
Driving ITT7400 series TTL from ITT930 series DTL
necessitates a reduction of the full fan-out from 8
to 3 for standa(d'igates and from 25 to 20 for
buffers. Increas~d' f~n-out can be achieved with
standard DTL gates by using an additional pull-up
resistor.
SYMBOLS AND THEIR DEFINITIONS
Fan-out
ICCL
Load capacitor iri switching test circuit
(includes probe and jig capacitance):
Number of unit loads an output car)
drive.
Maximum clOck frequency.
Supply current for highest dissipation
logic state.
Supply current for lowest dissipation
logic:; state.
Input forward current.
Input reverse. current.
Output short circuit current.
Output leakage current.
Low state output current.
'i OH
ICC
IIN+
IIN­
Pdyn
RL
TA
th
th+
thtcp
tp
tpo
tpd+
t-min
t sp+
tsp -
VCC
VH
V IH
VIL
VOL
V OH
VOH(M).
VIN
V OUT
VT+
VT-
WIRED-OR
High state output current.
Supply current.
Input current at VT+
Input current at VT­
Dynamic power dissipation.
Load resistor in switching test circuit.
Ambient temperature.
Input hold time ..
Logical '1' hold time.
Logical '0' hold time.
, Clock pulse width.
Preset,or clear pulse width.
Output pulse width.
Propagation delay to logical '1' on output.
Propagation delay to logical '0' on output.
State of output (or input) before the
active edge of the clock pulse.
State of output (or input) after the active
edge of the clock pulse.
Minimum width trigger pulse.
Logical '1' input set up time.
Logical '0' input set up time.
Supply voltage.
Hysteresis voltage.
Input high voltage to ensure VOL (or
VOH)" ,
Input low voltage to ensure VOH (or
VOL)"
Output low voltage.
Output high voltage.
Output brl,lakdown voltage of open
collector device.
Voltage at an input.
Voltage at an output.
Positive edge threshold voltage.
Negative edge threshold voltage.
The commoning of open collector outputs
with a pull-up resistor to perform
the AN D, function.
"Output'level dependent on device logic as found
from truth table.
3-11