ITT - Index of

ITT
ITT5476, ITT7476
DUALJ-K MASTER-SLAVE FLIP-FLOPS
WITH PRESET AND CLEAR
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SEMICONDUCTORS
I
DUAL J-K MASTER-SLAVE FLIP-FLOPS
WITH PRESET AND CLEAR
The ITT7476 J-K flip-flop is based on the masterslave
principle. Inputs to the master section are
controlled by the clock pulse. The clock pulse also
regulates the state of the coupling transistors which
connect the master and slave sections. The sequence
of operation is as follows:
DUAL-iN-LINE PACKAGE
AND FLAT PACKAGE
PIN CONFIGURATION
(TOP VIEw)t
1. Isolate slave from master
2. Enter information from J and K inputs to master
3. Disable J and K inputs
4. Transfer information from master to slave.
logic
TRUTH TABLE
(Each Flip-Flop)
tn t n+1
J K a
0 0 an
0 1 0
1 0 1
1 1 5 n
N(ltes: 1. tn = Bit time before clock pulse.
2. tn+ 1 .'" Bit time after clock pulse.
POSITIVE
LOGIC:
LOW INPUT TO PRESET SETS Q TO LOGICAL I
LOW INPUT· TO CLEAR SETS Q TO LOGICAL 0
CLEAR. AND PRESET
ARE INDEPENDENT OF CLOCK
tplN ASSIGNMENTS FOR THESE CIRCUITS ARE THE SAME
FOR ALL PACKAGES.
2 . 3
H.IGH~ ..... .
1 4
LOW
CLOCK WAVEFORM
recommended operating conditions Min Nom Max Unit
Supply Voltage Vec: tTI5476 Circuits .......................................................................... 4.5 5 5.5 V
ITI7476 Circuits ..........,............................................................... 4.75 5 5.25 V
Operating Free-Air Temperature Range, TA: ITT5476 Circuits ,................................ -55 25 125 DC
ITI7476 Circuits ................................. 0 25 70 DC
Normalized Fan-Out From Each Output, N ...................................................................... 10
Width of Clock Pulse, tp(clock) .......................................................................................... 20
Width of Preset Pulse, tp(preset) ....................................................................................... 25
~~~~h ;:t~:;~;~,I::~:~~cl.~.a.~~ ........................................................:: ..::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::: ~tp~c~OCk)
Input Hold Time, thold ........................................................................................................ 0 ns
ns
ns
ns
3-106