ITT - Index of

ITT9093, ITT9094, ITT9097, ITT9099
DUALDTL MASTER-SLAVE J-K FLIP-FLOPS
NOTES:
1. Positive logic: 0= L. 1 = H is shown.
2. With synchronous entry. output changes occur as
clock level changes from High to Low. For operation
in accordance with the table. J and K inputs should
normally be changed while the clock is low. and
maintained while the clock is high.
3. Asynchronous entry overrides synchronous entry. regardless
of clock level. If So and CD are both low.
then both go high simultaneously. final condition
cannot be predicted. For proper operation. the So
or CD terminals must be held in the low state for
at least 50 nanoseconds.
4. From circuit symmetry. the So and CD pin designations
may be interchanged by interchanging the
J and K. and also the Q and Q pin designations. Thus.
the 9093-9094 may be used as a dual flip-flop having
CD terminals available. and the 9097-9099 may
be used as a dual flip-flop having separate CD terminals
and a common So terminal. All rules for
ITT945 apply to ITI9093 and 9099. All rules for
ITT948 apply to ITI9094 and 9097.
5. Refer to the ITT945/948 for typical operating characteristics.
ASYNCHRONOUS ENTRY
SYNCHRONOUS ENTRY
Inputs Outputs Inputs Output
TRUTH TABLES
So CD a a J K On+1
0 0 1 1 0 0 an
0 1 1 0 0 1 0
1 0 0 1 1 0 1
1 1 No Change 1 1 an
O.lMF I
r-----
r .-__...---,
+5.0 V
R
TPD TEST CIRCUIT
IN9162K
4-38