ITT - Index of

Series ITT9000-1, ITT9000-5
HIGH SPEED TTL
9022 SCHEMATIC DIAGRAM VCC
Vcc=Pln 14
Gnd=Pin 7
SYNCHRONOUS BCD COUNTER
APPLICATIONS
DIVIDE BY TEN COUNTER
IN....------.----h===:::::;-] r+====+===::;===l=t---- 1/5
1/10
VCC
01 02 04 08
Two TTL 9020 Dual Flip-Flops require no additional gating
to produce a fully synchronous 8421 code BCD Counter.
Two TTL 9020 Dual Flip-FlOps require no additional
gating elements to produce divide by ten circuit with a
square 'wave divide by ten output and a divide by five.
output.
BINARY COUNTER WITH ASYNCHRONOUS PARALLEL LOAD AND CLEAR
- PARALLEL INPUT -
ONES TRANSFER ENABLE ----...,-!-----.,.-\------'t4-----,
COUNT ENABLE --.---+-----1---+-.---+---.
COUNT INPUT -+'O'----+-f-J
MASTER CLEAR ----......---,f::--.2;~--'-+.Q2----....... ~"'Q4--'~---.J
- PARALLEL OUTPUT -
Binary counter using synchronous 2
bit stages with trickle down between
stages illustrates method of utilizing
dual JK flip-flops having common
clocks in counter applications.
3-306