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<strong>ITT</strong>5474, <strong>ITT</strong>7474<br />

DUAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS<br />

SWITCHING CHARACTERISTICS. Vee = 5V. TA = 25°e. N = 10<br />

Parameter Min Typ , Max Unit Test Conditions<br />

fmax Maximum clock frequency 15 25 MHz CL = 15 pF. RL = 400 &1<br />

tsetup Minimum input setup time 15 20 ns CL = 15pF.RL =400&1<br />

thold Mihimum input hold time 2 5 ns CL = 15pF.RL =400&1<br />

tpd1 Propagation delay time to logical 25 ns CL = 15pF.RL =400&1<br />

1 level from clear or preset to<br />

output<br />

tpdO Propagation delay time to logical 40 ns CL = 15 pF. RL = 400 &1<br />

o level from clear or preset to<br />

output<br />

tpd1 Propagation delay time to logical 10 14 25 ns CL = 15 pF. RL = 400 &1<br />

1 level from clock to output<br />

tpdO Propagation delay time to logical 10 20 40 ns CL = 15 pF. RL = 400 &1<br />

o level from clock to output<br />

1 All typical values are atVcc = 5V. TA = 25°C.<br />

2 For conditions shown as MIN or MAX. use the appropriate value specified under recommended operating conditions<br />

for the applicable device type.<br />

3 Not more than one output should be shorted at a time.<br />

schematic (each flip-flop)<br />

PRESET ...... _-...... _--4--~-----......<br />

TO OTHER<br />

CLEAR t-+-_--..J<br />

CLOCK~+-+-~-..J<br />

TO OTHER<br />

FLIP·FLOP<br />

NOTE: Component values shown are nomlrw!.<br />

3-101

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