ITT - Index of

ITT5472, ITT7472
J-K MASTER-SLAVE FLIP-FLOPS
E LECTR I CAL CHARACTE R ISTI CS over recommended operating free-air temperature range
(unless otherwise noted)
Parameter Min Typl Max Unit Test Conditions 2
Vin(l) Input voltage required to ensure 2 V
logical 1 at any input terminal
Vin(O) Input voltage required to ensure 0.8 V
logical 0 at any input terminal
VI Input elamp Voltage -1.5 V Vee = MIN.II = -12mA
Vout(1) Logical 1 output voltage 2.4 3.5 V Vee = MIN.lload = -400uA
Vout(O) Logical 0 output voltage 0.22 0.4 V Vee = MIN. Isink = 16mA
lin(O) Logical 0 level input current at -1.6 mA Vee = MAX. Vin = O.4V
Jl.J2.J3. Kl.K2.orK3
lin(O) Logical 0 level input current at -3.2 mA Vee = MAX. Vin = 0.4V
preset. clear. or clock
lin(l ) Logical 1 level input current at 40 uA Vee = MAX. Vin = 2.4V
J 1 . J2. J3. K 1. K2. or K3
1 mA Vee = MAX. Vin = 5.5V
lin(l ) Logical 1 level input current at 80 uA Vee = MAX. Vin =.2.4V
p reset. clear. or clock
1 mA Vee = MAX. Vin = 5.5V
lOS Short-circuit output current 3 -20 -57 mA Vee = MAX. ITT5472
-18 -57
Vin = 0
ITT7472
lee Supply current 10 20 mA Vee = MAX. Vin = 5V
1 All typical values are at Vee = 5V. TA = 25°e.
2 For conditions shown as M IN or MAX. use the appropriate value specified under recommended operating conditions
for the applicable device type.
3 Not more than one output should be shorted at a time.
SWITCHING CHARACTERISTICS. Vee = 5V. TA = 25°e. N = 10
Parameter Min Typ Max Unit Test Conditions
fmax Maximum clockfrequency 15 20 MHz eL= 15pF. RL = 400 [2
tpdl Propagation delay time to logical 16 25 ns eL = 15pF. RL = 400[2
1 level from clear or preset to
output
tpdO Propagation delay time to logical 25 40 ns eL = 15pF. RL = 400[2
o level from clear or preset to
output
tpd1 Propagation delay time to logical 10 16 25 ns eL = 15pF. RL = 400[2
1 level from clock to output
tpdO Propagation delay time to logical 10 25 40 ns eL = 15pF. RL = 400[2
o level from clock to output
3-94