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<strong>ITT</strong>5412, <strong>ITT</strong>7412<br />

TRIPLE 3-INPUT POSITIVE NAND GATES<br />

(WITH OPEN-COLLECTOR OUTPUT)<br />

ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range<br />

(unless otherwise noted)<br />

Parameter Min Typ' Max Unit Test Conditions 2<br />

Vin(1) Logical 1 input voltage required 2 V<br />

at both input terminals to ensure<br />

logical 0 (on) level at output<br />

Vin(O) Logical 0 input voltage required 0.8 V<br />

at either input terminal to ensure<br />

logical 1 (<strong>of</strong>f) level at output<br />

V 1 Input Clamp Voltage -1.5 V VCC = Min Ii = -12 mA<br />

lout( 1) Output reverse current 250 J.1A Vce = MIN. Vin(O) = 0.8V.<br />

Vout(1) = 5.5V<br />

Vout(O) Logical 0 output voltage (on 0.4 V Vee = MIN. Vin = 2V.<br />

level)<br />

Isink = 16 rnA<br />

linlO) Logical 0 level input current -1.6 mA VCC = MAX. Vin = O.4V<br />

(each input)<br />

linl1 ) Logical 1 level input current 40 J.1A Vce = MAX. Vin = 2.4V<br />

(each input)<br />

1 mA Vce = MAX. Vin = 5.5V<br />

leelO) Logical 0 level supply current g 16.5 mA Vce = MAX. Vin = 5V<br />

leC(1 ) Logical 1 level supply current 3 6 mA Vce = MAX. Vin = 0<br />

, All typical values are at Vec = 5V. T A = 25° C.<br />

2 For conditions shown as M IN or MAX. use the appropriate value specified under recommended operating conditions<br />

for the applicable device type.<br />

SWITCHING CHARACTER ISTICS, Vee = 5V. T A = 25°e<br />

Parameter Min Typ Max Unit Test Conditions<br />

tpdO Propagation delay time to logical 8 15 ns CL = 15pF. RL = 400 n<br />

o level<br />

tpd1 Propagation delay time to logical 35 45 ns CL = 15 pF. RL = 4 kn<br />

1 level<br />

3-40

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