ITT - Index of

ITT
ITT54H76, ITT74H76
DUALJ-K MASTER-SLAVE FLIP-FLOPS
- -----
SEMICONDUCTORS
DUAL J-K MASTER-SLAVE FLIP-FLOPS
These dual J-K flip-flops are based on the masterslave
principle. Inputs to the master section are
controlled by the clock pulse. The clock pulse also
regulates the circuitry which connects the master
and slave sections. The sequence of operation is
as follows:
1. Isolate slave from master
2. Enter information from J and K inputs to
master
3. Disable J and K inputs
4. Transfer information from master to slave.
Logical state of J and K inputs must not be allowed
to change when the clock pulse is in a high state.
DUAL -I N-LiNE PACKAGE AND FLAT PACKAGE
PIN CONFIGURATION (TOP VIEW)t
I
PRESET
I
CLEAR
VCC
2
. CLOCK
2
PRESET
2
CLEAR
IK
10
GND
2K
20
CLOCK WAVEFORM
POSITIVE LOGIC:
LOW INPUT TO PRESET SETS 0 TO LOGICAL I
LOW INPUT TO CLEAR SETS 0 TO LOGICAL 0
CLEAR ANO PRESET ARE INDENPENDENT OF ClOCK
tplN ASSIGNMENTS FOR THESE CIRCUITS ARE THE
SAME FOR ALL PACKAGES.
lOW
tn
'n+l
logic
J K a
0 0 an
TRUTH TABLE 0 1 0
1 0 1
1 1 an
Notes:
1. tn = Bit time before clock
recommended operating conditions
Supply voltage Vee
Normalized fan-out from each output N
Width of clock pulse. tp(clock)
Width of preset pulse. tp(preset)
. Width of clear pulse. t p(c1ear)
Input setup time. tsetup
Input hold time, t hold
Operating free-air temperature range. T A
2 In+l "" Bit time after clock pulse
ITT54H76
ITT74H76
Min Nom Max Min Nom Max Unit
4.5 5 5.5 4.75 5 5.25 V
10 10
12 12 ns
16 16 ns
~tp(clock)
~tp(clock)
0
1 0
-55 25 125 0 25 70 °e
3-283