ITT - Index of

~ ITT _________ U_N_'V_E
SEMICONDUCTORS
ITT74124
.. R ... S_A_L_PU_LS_E_G_EN_ER_A_T_O_R
UNIVERSAL PULSE
GENERATOR
• Delayed Pulse Generator.
Controllable high stability oscillator.
.. Applications include clock generator, Timing
pulse generation, Synchronized oscillator,
and pulses frequency divider.
o Outputs available from the two incorporated
Cascade Monostables.
No jitter self start.
., Complete output waveforms.
" Positive Schmitt Trigger input.
TIMING {::: ~
CIR9UIT EXT R
INT R
NEGATIVE
TRIGGER
POSITIVE
TRIGGER
Q,OUTPUT
GND
DUAL- IN-LINE PACKAGE
PIN CONFIGURATION
(TOP VIEW)
VCC
INTR} TIMING
EXT C CIRCUIT
EXT R 2
EXT C
Q20UTPUT
02 OUTPUT
PIN CONFIGURATION (top view)
INHIBIT OSC.
INPUT
" Delays and pulse widths from 35 ns to 40
second.
- FEEDBACK CONNECTION
~O--"""'-=j
POSITIVE
TRIGGER
LOGIC DIAGRAM
Mode
OSCILLATOR
MODE
DELAYED
PULSE
MODE
STABLE
STATE MODE
TRUTH TABLE
Inputs
Outputs
During Time Period:
INH POS NEG Tl T2
OSC TRIG TRIG 01 02 02
1 0 X JI.. JI.. -U-
1 X 1 JI.. ..n... ""Lr
0 t 0 J"1.. ..n... "1J""
0 1 t J"1.. ..n... l.J
ALL OTHER 0 0 1
LEVELS
6 1 ~3
\ EXTERNAL e, R
EXTERNAL e
9 10 II 12 13
\. .... EXTERNAL etR
EXTERNAlC
Notes:
t = Transition from 0 to 1.
+ = Tra nsition from 1 to O.
X = Indicates that O. 1 or any transition may be present.
...n..= 1 level pulse of width = timing period T 1 or T 2·
1-f= 0 level pulse of width = timing period T 2.
Timing period T 1 set by timing,circuit 1.
Timing period T 2 set by timing circuit 2.
3-158