ITT - Index of

ITT
ITT54195, ITT74195
4-81T PARALLEL-ACCESS SHI FT REG ISTERS
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SEMICONDUCTORS
4-BIT PARALLEL-ACCESS SHIFT REGISTERS
• Synchronous Parallel Load
• Positive Edge-Triggered Clocking
• Parallel Inputs and Outputs from
Each Flip-Flop
• Direct Overriding Clear
• J and K Inputs to First Stage
• Complementary Outputs from Last Stage
CLEAR
SERIAL{J
INPUTS R
DUAL-IN-LiNE PACKAGE
AND FLAT PACKAGE
PIN CONFIGURATION
(TOP VIEW)t
Vee
OUTPUTS
PARALLEL{:
INPUTS
e
o
SHIFT/
LOAD
These 4-bit registers feature parallel inputs. parallel
outputs. J-K serial inputs. shift/load control input.
and a direct overriding clear. The registers have two
modes of operation:
Parallel (Broadside) Load
Shift (In direction QA toward QD)
Parallel loading is accomplished by applying the
four bits of data and taking the shift/load control
input low. The data is loaded into the associated
flip-flop and appears at the outputs after the
positive transition of the clock input. During
loading. serial data flow is inhibited.
Shifting is accomplished synchronously when the
shift/load control input is high. Serial data for this
mode is entered at the J-K inputs. These inputs permit
the first stage to perform as a J-K. 0-. or T-type
flip-flop as shown in the truth table.
These shift registers are fully compatible with most
other TTL and DTL families. All inputs are buffered
to lower the drive requirements to one normalized
Series 54174 load. including the clock input. Maximum
input clock frequency is typically 39
megahertz and power dissipation is typically 195
milliwatts. The ITT54195 is characterized for operation
over the full -military temperature range of
-55°C to 125°C; the ITI74195 is characterized
for operation from O°C to 70° C.
POSITIVE LOGIC: SEE DESCRIPTION
, Pin assignments for these circuits are the
same for all packages.
TRUTH TABLE
Inputs a.!. tn Outputs at t n+1
J K QA QB QC Q D QD
L H QAn QAn QBn QCn QCn
L L L QAn QBn QCn QCn
H H H QAn QBn QCn QCn
H L QAn QAn QBn QCn QCn
H = high level. L = low level
Notes: A. tn = bit time before clock pulse
B. tn+ 1 = bit time after clock pulse
C. QAn = state of QA at tn
absolute maximum ratings over operating free-air
temperature range (unless otherwise noted)
Supply voltage. V CC (see Note 1) ........................... 7V
Input voltage (see Note 1) .................................... 5.5V
Operating free-air temperature range:
ITI54195 Circuits ......................... - 55°C to 125°C
ITT74195 Circuits .................................. O°C to 70°C
Storage temperature range ........... -65°Cto 150°C
Note:
1. Voltage values are with respect to network
ground terminal.
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