ITT - Index of

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SEMICONDUCTORS
SMALL' SIGNAL CHIPS AND WAFERS
INTRODUCTION
ITT has a wide selection of planar transistor chips
and wafers available for those who require devices
in this form. Since the large number of JEDEC
specifications are derived from a few chip types,
many differing applications can be satisfied with
a relatively small quantity of basic chip families.
SPECIFICATIONS
The accompanying DC parameters identifying
each family are tested on each chip in the wafer.
These are the probe speCifications. As shipped
from our factory, THE PROBE PARAMETERS ARE
GUARANTEED TO AN AQL = 2.5%.
The design parameters such as V CE(SAT)" ton, toff,
COb, etc. are not probed. These characteristics
can best be tested after the chip is suitably
mounted; and, therefore, have little significance
in chip form.
The chips will have a high yield to the specified
limits. The actual yield will vary with the mechanical
techniques used to assemble the device,
and the type of package used.
In all cases, the lowest useable voltage and the
lowest useable hFE should be chosen in specifying
chip parameters. This will provide the highest
possible yield and the most economical design.
USE
The entire wafer is manufactured with approximately
3000 A ° of gold for die attach to a suitable
substrate or base. Recommended die attach temperature
for all families is 450°C, maximum. 9,000
to 12,000 angstroms of aluminum are deposited
on the chip for metalization purposes. ITT recommends
aluminum wire for connection to the aluminum
base and emitter bonding pads. Ultrasonic
techniques may be used for the, wire-bond operation.
PACKAGING FOR SHIPMENT
Chips will be shipped in appropriate containers,
with the devices packaged to protect them from
damage in shipment. Wafers will be shipped in a
similar manner. Unless otherwise specified, wafers
will not be scribed prior to shipment.
CROSS REFERENCE CHART
The list of JEDEC specifications, together with
the respective chip specification, will provide a
means of ordering the proper chip required in
an application. This chart is not exhaustive, and
is provided as a guide. Specific requirements may
necessitate a different chip specification from
available JEDEC "2N" numbers. In such cases,
the accompanying list of chip parameters will
provide the necessary information.
ORDERING
All chips and wafers should be ordered according
to the alpha-numeric coding system referred to
in the speCification chart. The four-digit geometry
family, together with the voltage letter and DC
gain number (from the accompanying geometry
parameter chart) will completely determine the
specification which ITT will provide. A third letter
specifies in which form, chip or wafer, the product
is to be shipped.
E.G.:
IDENTIFICATION
Q Family
Q 1.- § §!.l\Q ~
C = Chi
Voltage Gain W = Wafer
All small-signal transistor dice will be identified
by the appropriate four-digit family number together
with the particular classification code for
voltage and current gain.
By way of example:
The 2N2222 is a "0018" chip. The voltage class
is "M," the current gain is "A." Therefore, when
ordering a 2N2222 in chip or wafer form, the
correct part would be a "0018MA" chip. This
method applies to dice and to a wafer which has
been tested 1 00%.
If a wafer is needed which does not require all
the chips to be tested, then the alpha-numeric
suffix will apply. For a 2N2222 device, in wafer
form, sample probe-tested only, the proper part
number will be a "0018S1."
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