ITT - Index of

ITT
ITT5473, ITT54107, ITT7473, ITT74107
DUAL J-K MASTER-SLAVE FLI PS-FLOPS
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SEMICONDUCTORS
DUAL J-K MASTER-SLAVE FLIPS-FLOPS
DUAL-IN - LINE PACKAGE
PIN CONFIGURATION
(TOP VIEW)
ITT5473. ITT7473
FLAT PACKAGE
PIN CONFIGURATION
(TOP VIEW)
ITT541 07. ITT741 07
DUAL - IN - LINE PACKAGE
PIN CONFIGURATION
(TOP VIEW)
@Q
@o
GND
CLOCK
VCC@
CLOCK 0
CLEAR®
@~ND
@)K
POSITIVE LOGIC:
LOW INPUT TO CLEAR SETS 0 TO LOGICAL O.
CLEAR IS INDEPENDENT OF CLOCK.
These J-K flip-flops are based on the master-slave
principle. Inputs to the master section are controlled
by the clock pulse. The clock pulse also regulates
the state of the coupling transistors which
connect the master and slave sections. The se­
. quence of operation is as follows:
HIGH
1. Isolate slave from master
2. Enter information from J and K inputs
to master
3. Disable J and K inputs
4. Transfer information from master to
slave.
logic
TRUTH TABLE
(Each Flip-Flop)
tn t n +1
J K Q
0 0 Qn
0 1 0
1 0 1
1 1 On
Notes:
1. tn = Bit time before clock pulse.
2. tn+ 1 = Bit time after clock pulse.
lOW
CLOCK WAVEFORM
3-96