ITT - Index of

I mm ..I....L
ITT54/74192,ITT54/74193
SYNCHRONOUS 4-81T UP-DOWN COUNTER
-o/SEMICONOUCTORS --------------------
SYNCHRONOUS 4-B'T UP-DOWN
CO U NTE R (dual clock with' clea'r)
• Cascading Circuitry Provided Internally
• Guaranteed fanout of 10 TTL loads over
the full temperature range and supply
voltage ranges.
• High capacitive drive capability.
• Individual Preset to Each Flip' Flop.
• Typical power dissipation of 325 mW
• The input/output characteristi'cis provide
easy interfacing with DTL930, TTL9000,
TIL7400 and MSI families .
•• Input clamp diodes limit high speed line
termination effects ",.'
• Fully Independent Clear Input
• Typical Maximum Input Count
Frequency .•... 32 MHz
DUAL -IN-LINE PACKAGE
AND FLAT PACKAGE
PIN CONFIGURATION
(TOP VIEW)
II }
'-----I .)
},~"
} OUTPUTS
INPUTS
LOGIC LOW INPUT TO LOAO SETS
OA=A , 0 8 =8, atc . a 0=0
The M SI ITT5417 4192 is a synchronous \J,p(down
decade counter with separate up/down clockS'. parallel
load (asynchronous) facility. two terminal
count outputs for multi-decade operation. and a"~
asynchronous overriding master reset
The MSI ITT54174193 is a synchronous up/down
4-bit binary counter with separate up/down clocks.
parallel load (asynchronous) facility. terminal count
outputs for multi-decadeTPperations. and an asynchronous
overriding master reset.
Counting is synchronous. with the outputs changing
state after the low to high transition of either
the count-up clock (CPU) or count-down clock
(CPO). The direction of counting is determined by
which clock input is pulsed while the other clock
input is high. (incorrect counting will occur if both
the count-up clock and count-down clock inputs
are pulsed simultaneously.) The counter will respond
to a clock pulse on either input by changing
to the next appropriate state of a binary sequence.
The counter hasra parallel load (asynchronous) facility
which pernjlits the counter to be reset. Whenever
the data e'~able (Pl;) input is low. the information
present on the parallel data inputs (P A- PB•
PC. PO) will be loaded into the counter and appear
on the outputs independent of the conditions of the
clock inputs. When the data enable input goes low.
this information is stored in the counter and when
the counter is clocked it changes to the next appropriate
state in the counts sequence. The data
inputs are inhibited when the data enable is high
and have no t;lffect on the counter.
The terminal count-up (T!=:U) and terminal countdown
(TC O ) outputs (Carry and Borrow respectively)
allow multistage binary counter operations
without additional logic. The counters are cascaded
by feeding the terminal count-up output to the
count-up clock input and the terminal'count-down
output to the count-down input of the following
counter.
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