ITT - Index of

Series ITT9000-1, ITT9000-5
HIGH SPEED TTL
9005-1. 9006-1 AND 9008-1
OUTPUT CURRENT VERSUS
OUTPUT VOLTAGE
(OUTPUT LOW)
.00
Vcc' S'ov
IN~UTS OPEN
160 TS'C
120
k
~ 2~
; O'C
~ L
-55'C
'WORST CASE TURN OFF DELAY
OF NON EXTENDABLE GATE
.. VERSUS AMBIENT TEMPERATURE ..
Yee' S,OY
SEE FlU
80
~.~1~
.0
I
~ I
I
I
°0 0.4 0.8 1.2 1.6 2.0
Your - ounUT VOLTAGE - VOLTS
I---'
WORST CASE TURN ON DELAY
OF NONEXTENDABLE GATE
..VERSUS AMBIENT TEMPERATURE
40
:
I
~ 32
111
! 2.
,,~~. ~1 c,:\~ P'" ~ ~ 16
I
I-
1II •• ~1 Ct·'s"
o
-S5 25
125
TA - AMBIENT TEMPERA1\IfE -Ie
J.. r'
-- Vcc' 5.0V
\
SEE FIG. 7
I
f- .... - ~ ~Tc;,.~o" I-
~
_.
i' .1.
o
-55
~
- .:::
AlAx. AT c;",,,,
25
"N. AT cL,rSpF --
lA-AMBIENT TEIlPEATURE-'C
WORST CASE TURN ON DELAY
OF EXTENDABLE GATE VERSUS
.s AMBIENT TEMPERATURE
~ ~. . 1 .... L...l Vee' 5.OV
_\. '. r· --r SEE FIG .•
'0 h~--+-t--t-i-H
I
~ 32 ,I I r
.. 'l\r ; .. -1--+_.+_+_
I!It-t~·+; ~ .. L
• 24
"., AT CL I J5~"
I ·tt '_ .. r-
I. I. r--i- "".2.
1- . "'J X-ATCL'I5,,!-'
SC 1
F=:tl:~~~~"CTCl~I~5"±=~~--~
~5's 25 125
T A - AMarNT TEMPERATIJIE - "e
40 h-+-+-++-+
I
~ 321--+-+--+-+--:1.
~M~-+-t~~+-~~
~ .,.
j
~~~-+~-+-+-t-4
r A - AMBIENT TEMPERATURE -'e
J·K FLlP·FLOPS - 9000, 9001, DUAL J·K FLIP·FLOPS - 9020, 9022
The TTL 9000 series has four flip-flops to
satisfy the storage requirements of a logic
system. All are master-slave JK designs and
have the same high speed and high noise
immunity as the rest of the 9000 series. As with
the gates, all inputs have diode clamps to
further engance the noise immunity.
The JK type flip-flop was chosen for all flip-flop
elements in this family because of its inherent
logic power. The input function required to
produce a given sequency of states for a JK
flip-flop will, in general, contain more "don't
care" conditions than the corresponding
function for an RDdlip-dlop. These additional
"don'.t care" conditons will, in most cases,
reduce the amount of gating elements required
to implement the input function.
The master-slave design offers the advantage
of a DC threshold on the clock input initiating
the transition of the outputs, so that careful
control cif clock pulse rise and fall times is not
required.
D;;lta is accepted by the master while the clock
is in the low state. Refer to the truth table for
definition of "ONE" and "ZERO" data. Transfer
from the master to the slave occurs on the low
to high transition of the clock. When the clock
is high, the J and K inputs are inhibited.
A jOint (JK) input is provided for all flip-flops in
this family. This common input removes the
'necessity of gating the clock signal with an
external gate in many applicaitons. This not
only reduces package count, but also reduces
the possibility of clock skew problems, since
with internal gating provided, all flip-flops may
be driven from a common clock line. Several
TTL drivers may be used in parallel to drive this
common clock line, if the load exceeds the
F.O. capability of the 9009 buffer.
The asynchronous Inputs provide ability to
control. the state of the flip-flop independent of
static conditions of the clock and synchronous
inputs. Both asynchronous set and clear are
provided on all flip-flops except the 9020,
3-298