ITT - Index of

ITT9309
MSI Dual Four-Input Multiplexer
Figure 15 - MULTIPLEXING TWO BITS
FROM SIXTEEN SOURCES
This diagram shows the interconnection of five
ITT9309 dual four bit multiplexers to provide
switching of two bits of data from one of
sixteen words onto a tow bit data buss. The
selection of which word will be transferred to
the buss is made by the address supplied to the
So, S1, S2, and S3 inputs. As an example: if
twelve bit words are to be transferred to a
twelve bit buss, the above diagram would be
repeated six times. Notice that the negative
outputs are used at both levels resulting in the
assertion output (negation of the negation) at a
higher speed due to the fact that the through
delay is less on the negation output.
If the word selecting address is held in four TTL
flip flops (two dual packages) enough load
capability is available to select between
sixteen, sixteen bit words.
~ ---;1>--+-+--+--+----+-1--____ ..,.., .. "', .... UIII
OPERATION CODE LIST
S, S, INSTRUCTION
o 0 SHIFT LEFT
1 0 AOD
o 1 SHIFT RIGHT
1 1 COMPLEMENT
H~···l··.
L~"O"
Figure 16- GENERAL PURPOSE
ACCUMULATOR
A fast, general purpose accumulator for
computer applications is capable of: 1) shift
left; 2) add; 3) shift right and 4) complement
operations. Only three packages are required to
construct two stages of the general purpose
accumulator shown above.
The D input capability of the ITT9022 is utilized
here to allow each flip flop of the accumulator
to accept the data as presented by the ITT9309
multiplexer.
Under the operation code instructions the
multiplexer provides an input to the ITT9022·
from: 1) adjacent stage to the right for a shift
left operation; 2) adjacent stage to the left for a
shift right operation; 3) output of adders for
add operation and 4) Q outputs of ITT9022 for
the com.plement operation. The operation code
at the right of Figure 18 shows the instruction
codes to perform the various operations. The
accumulator should be capable of 20-25MHz
operation.
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