ITT - Index of

ITT5476, ITT7476
DUALJ-K MASTER-SLAVE FLIP-FLOPS
WITH PRESETAND CLEAR
ELECTRICAL CHARACTERISTICS. TA = ooe to 70 0 e (unless otherwise noted)
Parameter Min Typ' Max Unit Test Conditions 2
Vin(1 ) Input voltage required to ensure 2 V
logical 1 at any input term inal
Vin(O) I nput voltage required to ensure 0.8 V
logical 0 at any input terminal
V 1 Input Clamp Voltage -1.5 V Vee = MIN. Ii = -12mA
Voutll) Logical 1 output voltage 2.4 3.5 V Vee = MIN. Iload = -400uA
VoutlO) Logical 0 output voltage 0.22 0.4 V Vee = MIN. Isink = 16mA
linlO) Logical 0 level input current at -1.6 mA Vee = MAX. Vin = O.4V
J or K
linlO) Logical 0 level input current at -3.2 mA Vee = MAX. Vin = 0.4V
clear. preset. or clock
linll ) Logical 1 level input current at 40 uA Vee MAX. Vin 2.4V
JorK 1 mA Vee = MAX. Vin = 5.5V
lin(1) Logical 1 level input current at 80 uA Vee = MAX. Vin = 2.4V
clear. preset. or clock
1 mA Vr:r: - MAX. Vin - 5.5V
lOS Short-circuit output current 3 -20 -57 mA Vee = MAX. ITT5476
V· = 0 I ITT7476
18 57
In .
ICC Supply current leach flip-flop) 20 40 mA Vee - MAX
SWITCHING CHARACTERISTICS. Vee = 5V. TA = 25°e. N = 10
Parameter Min Typ Max Unit Test Conditions
fmax Maximum clock frequency 15 20 MHz eL = 15 pF. RL = 400.0.
tpdl Propagation delay time to Ipgical 16 25 ns eL = 15 pF. RL = 400.0.
o level from clear or preset.to
output
tpdO Propagation delay time to logical 25 40 ns eL - 15 pF. RL - 400.0.
1 level from clear or preset to
output
tpdl Propagation delay time to logical 10 16 25 ns eL - 15 pF. RL - 40011.
1 level from clock to output
tpdO Propagation delay time to logical 10 25 40 ns eL = 15 pF. RL = 400.0.
o level from clock to output
, All i I -
0
typ ca values are at Vee 5V. T A 25 e.
2 For conditions shown as MIN or MAX. use the appropriate value specified under recommended operating c·onditions
for the applicable device type.
3 Not more than one output should be shorted at a time.
3-107