ITT - Index of

I mm
-___L_L ________________
SEMICONDUCTORS
SYNCHRONOUS 4-BIT COUNTERS
ITT54160 THRU ITT54163
ITT74160 THRU ITT74163
S.Y_N_CH_R_O_N_O.U_S __ 4_-B_IT __ CO __ U_NT_E_R_S
ITT54160. ITT54161. ITT74160. ITT74161 •..• SYNCHRONOUS COUNTERS WITH DIRECT
CLEAR
ITT54162. ITT54163. ITT74162. ITT74163 ... FULLY SYNCHRONOUS COUNTERS
• Internal Look-Ahead for Fast Counting
Schemes
• Carry Output for n-Bit Cascading
• Synchronous Counting
• Synchronously Programmable
• Load Control Line
• Diode-Clamped Inputs
• Typical Maximum Input Clock Frequency
... 32 MHz
These synchronous, presettable counters feature an
internal carry look-ahead for application in highspeed
counting schemes. The ITT54160, ITT-
54162, ITT74160, and ITT74162 are decade
counterS and the ITT54161, ITT54163, ITT74161.
and ITT74163 are 4-bit binary counters. Synchro-­
nous operation is provided by having all flip-flops
clocked simultaneously so that the outputs change
coincident with each other when so instructed by
the count-enable inputs and internal gating. This
mode of operation eliminates the output counting
spikes which are normally associated with asynchronous
(ripple clock) counters. A buffered clock
input triggers the four J-K master-slave flip-flops
on the rising (positive-going) edge of the clock input
waveform.
These counters are fully programmable; that is, the
outputs may be preset to either state. As presetting
is synchronous, placing a low level on the load input
disables the counter and causes the outputs to
agree with the data inputs after the next clock
pulse. The clear function for the ITT54160, ITT-
54161, ITT74160, and ITT74161 is asynchronous
and a low level at the clear input sets all four of
the flip-flop outputs low regardless of the state of
the clock. The clear function for the ITT54162, ITT-
54163, ITT74162, and ITT74163 is synchronous
and a low level at the clear input sets all four of
the flip-flop outputs low after the next clock pulse.
r:
DATA
INPut
ENABLE
P
DUAL-IN-LINE PACKAGE
AND FLAT PACKAGE
PIN CONFIGURATION
(TOP VIEW) t
POSITIVE LOGIC: SEE DESCRIPTION
tplN ASSIGNMENTS FOR THESE CIRCUITS ARE THE SAME
FOR ALL PACKAGES.
This synchronous clear allows the count length to
be modified easily as decoding the maximum count
desired can be accomplished with one external
NAND gate. The gate output is connected to the
clear input to synchronously set the counter to
0000 (LLLL).
The carry look ahead circuitry provides for
cascading counters for n-bit synchronous applications
w.ithout additional gating. Instrumental in
accomplishing this function are two count-enableinputs
and l!- carry output. Both count-enable inputs
(P and T) must be high to count, and input T is
3-196