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ITT - Index of

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<strong>ITT</strong>9304<br />

MSI Dual Full' Adder<br />

APPLICATIONS - The <strong>ITT</strong>9304 dual adder has<br />

been designed to be useful in a wide variety <strong>of</strong><br />

applications such as addition, parity generation<br />

and checking, code conversion, majority<br />

gating and other applications for which this<br />

combination <strong>of</strong> logic gates may be useful. The<br />

multifunction capabilities <strong>of</strong> the <strong>ITT</strong>9304 dual<br />

adder can be seen from reference to the<br />

applications shown.<br />

~ ~<br />

-OR-<br />

Ie<br />

9304<br />

B<br />

FA 2<br />

A<br />

sse<br />

Figure 12 - FUNCTIONAL BLOCK<br />

REPRESENTATION<br />

The principal <strong>of</strong> duality allows 2 ways <strong>of</strong><br />

representing each adder. The circuit is the<br />

same in both cases but the logic diagrams<br />

differ. The dual diagrams facilitate logic design<br />

and allow a greater understanding <strong>of</strong> the<br />

capabilities <strong>of</strong> the device.<br />

Figure 13 - RIPPLE CARRY<br />

PARALLEL ADDITION<br />

Shown above is a high speed ripple carry<br />

parallel addition scheme. Only one and-or-not<br />

gate delay is incurred at each stage allowing a<br />

typical addition speed <strong>of</strong> (N + 1) x 8 ns, where N<br />

is the number <strong>of</strong> bits in the word. A similar<br />

scheme will work if the negation inputs are<br />

used, and the design acts as a subtractor when<br />

the complement <strong>of</strong> one variable is provided.<br />

c<br />

400<br />

JOO<br />

~<br />

ii 200<br />

~<br />

~<br />

100<br />

,,I'<br />

o<br />

o<br />

PROPAGATION DELAY AND<br />

PACKAGE COUNT AGAINST<br />

WORD LENGTH FOR<br />

RIPPLE CARRY ADDITION<br />

~<br />

V<br />

",'S<br />

V V<br />

.f

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