ITT - Index of

ITT
ITT9308
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MSI Dual Four-Bit Latch
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SEMICONDUCTORS
u~SI DUAL FOU R-BIT
lATCH
Active Level Low Enable Gate Inputs
Overriding Master Reset
25 ns Through Delay
The Input/Output Characteristics Provide
Direct Interfacing With ITT DTL and TTL
Input Clamp Diodes Limit High Speed Termination
Effects.
LOGIC DIAGRAM
23 4 6 8 10
~
E DO 0, 02 03
9308 4 BIT LATCH I
MR 110 0, 02 03
9
The MSllTT9308 is a Dual 4-Bit Latch designed
for general purpose storage applications in
high speed digital systems. The ITT9308 uses
TTL technology. All inputs .incorporate diode
clamps to ground to reduce negative line
transients. All outputs have active pull-up circuitry
to provide high capacitive drive and low
impedance outputs in both logic states to provide
good A.C. noise immunity.
ABSOLUTE MAXIMUM RATINGS
(above which the useful life may be impaired)
157911
14 15 16 18 20 22
DO 0, 02 03
9308 4 BIT LATCH 2
MR 110 0, 02 Q3
Conditions
Units
13 17 19 21 23
Storage Temperature
................-65 to + 150 C
Temperature (Ambient) Under
Bias ............-55 to + 155 C
Vee Pin Potential to Ground
Pin ..............-0.5 to + 7 Volts
Input Voltage (D.C.)
)see Note 1) .....-0.5 to + 5.5 Volts
Input Current (D.C.)
(SeeNote1) ... '" .-30to +5 mA
Voltage Applied to Outputs
(Output High) ..-0.5 to + Vee value
Output Current (D.C.)
(Output Low) ............ + 30 mA
NOTE 1: Either Input Voltage limit or Input Current limit is
sufficient to protect the inputs.
Vee = Pin 24
Gnd = Pin 12
Description of Latch Operation - Data can be
entered into the latch when both of the enable
inputs are low. As long as this logic condition
exists, the output of the latch will follow the
input. If either of the enable inputs goes high,
the data present in the latch at that time is held
in the latch and is no longer affected by the
data input.
The master reset overrides all other input
conditions and forces the outputs of all the
latches low when a low signal is applied to the
master reset input.
3-327