SIMPLORER User Manual V6.0 - FER-a

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136 Modeling with Circuit Components
Electrical Model
The model uses an electrical equivalent circuit as shown in the figure below.
There are two simulation levels regarding the electrical behavior. The level is set at the parameter
TYPE_DYN:
TYPE_DYN=0
Only the static behavior is calculated. The charges at the capacitances are ignored, no
switching behavior.
TYPE_DYN=1
In addition to the static behavior, charging and discharging of the junction and diffusion capacitance
are calculated. Values of parasitic capacitances at the terminals can be defined.
Electrical Behavior Level, Type DYN=0
For the calculation of the static FET current a distinction is made between the linear region
and the pinch-off region. The so-called saturation voltage is given with
Vsat A_FET ( VGS – VP) M_FET
= ⋅
The transition happens when the drain current satisfies the following equation
Isat k
-- ( VGS – V
2
P)
N_FET
= ⋅
Within the linear region the following equation is used
ID Isat ( 1 + KLM ⋅ VDS)
2 VDS ⎛ – ----------- ⎞ VDS
= ⋅ ⋅ ⋅ -----------
⎝ ⎠
and for pinch-off applies
ID =
Isat ⋅ ( 1 + KLM ⋅ VDS)
V sat
V sat
The model has a built-in fault detection. During the simulation the drain current, the voltage
drop from gate to source and from drain to source as well as the junction temperature are observed.
If their limitations are exceeded the model behavior changes. The switches controlled
by the FAULT flags are closed and the respective fault resistances determine the model characteristic.
If an over voltage across Gate-Source occurs, only RFAULT_GS comes into effect.
All other faults effect the RFAULT_DS.