SIMPLORER User Manual V6.0 - FER-a

Circuit Simulator Processing
SIMPLORER 6.0 — Manual 419
The circuit simulator is based on a modified nodal approach. For the solution of the differential
equation system, a numerical integration method (either the Euler or the trapezoidal algorithm)
is applied. The solution of nonlinear equations is done by the Newton-Raphson method;
the calculation of equation systems, linearized in the operating point, takes place by means
of LU factorization after Gauss.
An important feature of the applied solvers is the automatic time step control. This feature ensures
an adaptation of the calculation step width dependent on the active dynamic situation
in the system considered, in such a way that there is always an optimum between precision
of calculation and simulation speed. The time step limitations are user-defined by a minimum
and maximum time step. Through this same specification, the possible time step range for the
active simulation task is also determined:
TEND: Simulation duration
HMIN: Minimum time step width permissible
HMAX: Maximum time step width permissible
The limits for number of time steps are, consequently:
max step
tend hmin = ---------- and minstep =
-----------
The real number of time steps would be between these two boundaries. If the step width for
a specific time step is too large (automatically recognized), the circuit simulator requests a
cancellation of this time step, and it will be repeated with an adapted step width (also calculated
automatically). The necessary step cancellations are forwarded to a step width manager
and processed there.
Block Diagram Simulator Processing
t end
h max
Block diagrams are calculated according to the block transfer characteristics and in the sequence
of signal flow. Integrators are processed with the Euler method and according to the
principle of distributed integration.
For each block a certain sampling time can be defined by the user. Then the blocks are equidistantly
calculated only on these discrete times. The sampling time must be selected very
carefully. There may be dead time effects, especially in simulation models with different sampling
times.
If no sampling time is specified, the block diagram module runs with the same (variable) time
step as the circuit simulator (quasi continuous case). In this case, make sure that the block
diagram time constants are larger than those in the electrical circuit model. If no sampling
time is specified and there is also no electrical circuit in the model, the block diagram module
runs constantly with HMAX.
The observance of block diagram simulator calculation times is guaranteed by the predictive
time step control of the time step manager.