10.12.2012 Views

SIMPLORER User Manual V6.0 - FER-a

SIMPLORER User Manual V6.0 - FER-a

SIMPLORER User Manual V6.0 - FER-a

SHOW MORE
SHOW LESS

Create successful ePaper yourself

Turn your PDF publications into a flip-book with our unique Google optimized e-Paper software.

Circuit Simulator Parameters<br />

SECM.LDF<br />

(0.1…10)<br />

SECM.ITERATMAX<br />

(5…30)<br />

SECM.IEMAX<br />

1µ…100µ<br />

SECM.VEMAX<br />

1m…1<br />

Differences to Standard VHDL-AMS<br />

<strong>SIMPLORER</strong> 6.0 — <strong>Manual</strong> 405<br />

Local discretization error [%]. Defines the time step dependent on the<br />

dynamic of the circuit. A small error increases the precision but also<br />

the calculation time. This number itself gives no clue as to the precision<br />

of the overall result.<br />

Maximum number of iterations for one simulation step. If convergence<br />

problems occur, the calculation for the active simulation step will be<br />

stopped when the maximum value is reached without consideration of<br />

other error limits.<br />

Maximum current sum error. A very small value lead to accurate results,<br />

but convergence problems might be possible in the Newton integration<br />

method.<br />

Maximum voltage error. A very small value leads to accurate results,<br />

but convergence problems may occur using the Newton integration<br />

method.<br />

<strong>SIMPLORER</strong> Schematic<br />

• Model parameter in <strong>SIMPLORER</strong> style (no TIME, 'LEFT,…)<br />

• Vector elements in the property box of the model ({0,1,0,0}, "01010", 1=>5.0, 3=>4.0,<br />

other=>0.0) cannot be initialized.<br />

• No signals in <strong>SIMPLORER</strong> SML, therefore all <strong>SIMPLORER</strong> quantities creating events like<br />

a signal.<br />

• No difference between ports and generics in <strong>SIMPLORER</strong>.<br />

• No display of physical units (sec, hour, …) in a Display Elements.<br />

• Physical values in base units (Time in fs)<br />

• No C Interface.<br />

Structures<br />

• No port and generic map between blocks.<br />

Data types<br />

• No pointers.<br />

• No composite natures.<br />

• No quantity arrays simultaneous statements.<br />

Unsupported VHDL statements<br />

• Generate<br />

• Alias, Group<br />

• <strong>User</strong>-defined attributes<br />

• RESOLUTION function<br />

• LIMIT/TOLERANCE groups<br />

Unsupported attributes<br />

• Q'Tolerance<br />

• DT'Range<br />

• Terminal attributes

Hooray! Your file is uploaded and ready to be published.

Saved successfully!

Ooh no, something went wrong!