MMC2107 - Freescale Semiconductor

Freescale Semiconductor, Inc.
Signal Description
Signal Descriptions
4.5.9 Debug and Emulation Support Signals
These signals are used as the interface to the on-chip JTAG (Joint Test
Action Group) controller and also to interface to the OnCE logic.
4.5.9.1 Test Reset (TRST)
This active-low input signal is used to initialize the JTAG and OnCE logic
asynchronously.
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4.5.9.2 Test Clock (TCLK)
4.5.9.3 Test Mode Select (TMS)
4.5.9.4 Test Data Input (TDI)
4.5.9.5 Test Data Output (TDO)
This input signal is the test clock used to synchronize the JTAG and
OnCE logic.
This input signal is used to sequence the JTAG state machine. TMS is
sampled on the rising edge of TCLK.
This input signal is the serial input for test instructions and data. TDI is
sampled on the rising edge of TCLK.
This output signal is the serial output for test instructions and data. TDO
is three-stateable and is actively driven in the shift-IR and shift-DR
controller states. TDO changes on the falling edge of TCLK.
4.5.9.6 Debug Event (DE)
This is a bidirectional, active-low signal. As an output, this signal will be
asserted for three system clocks, synchronous to the rising CLKOUT
edge, to acknowledge that the CPU has entered debug mode as a result
of a debug request or a breakpoint condition. As an input, this signal
provides multiple functions.
MMC2107 – Rev. 2.0
Technical Data
MOTOROLA Signal Description 127
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