MMC2107 - Freescale Semiconductor

Freescale Semiconductor, Inc.
Timer Modules (TIM1 and TIM2)
Memory Map and Registers
Table 15-2. Timer Modules Memory Map
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Freescale Semiconductor, I
Address
TIM1
TIM2
Bits 7–0 Access (1)
0x00ce_0000 0x00cf_0000 Timer IC/OC select register (TIMIOS) S
0x00ce_0001 0x00cf_0001 Timer compare force register (TIMCFORC) S
0x00ce_0002 0x00cf_0002 Timer output compare 3 mask register (TIMOC3M) S
0x00ce_0003 0x00cf_0003 Timer output compare 3 data register (TIMOC3D) S
0x00ce_0004 0x00cf_0004 Timer counter register high (TIMCNTH) S
0x00ce_0005 0x00cf_0005 Timer counter register low (TIMCNTL) S
0x00ce_0006 0x00cf_0006 Timer system control register 1 (TIMSCR1) S
0x00ce_0007 0x00cf_0007 Reserved (2) —
0x00ce_0008 0x00cf_0008 Timer toggle-on-overflow register (TMTOV) S
0x00ce_0009 0x00cf_0009 Timer control register 1 (TIMCTL1) S
0x00ce_000a 0x00cf_000a Reserved (2) —
0x00ce_000b 0x00cf_000b Timer control register 2 (TIMCTL2) S
0x00ce_000c 0x00cf_000c Timer interrupt enable register (TIMIE) S
0x00ce_000d 0x00cf_000d Timer system control register 2 (TIMSCR2) S
0x00ce_000e 0x00cf_000e Timer flag register 1 (TIMFLG1) S
0x00ce_000f 0x00cf_000f Timer flag register 2 (TIMFLG2) S
0x00ce_0010 0x00cf_0010 Timer channel 0 register high (TIMC0H) S
0x00ce_0011 0x00cf_0011 Timer channel 0 register low (TIMC0L) S
0x00ce_0012 0x00cf_0012 Timer channel 1 register high (TIMC1H) S
0x00ce_0013 0x00cf_0013 Timer channel 1 register low (TIMC1L) S
0x00ce_0014 0x00cf_0014 Timer channel 2 register high (TIMC2H) S
0x00ce_0015 0x00cf_0015 Timer channel 2 register low (TIMC2L) S
0x00ce_0016 0x00cf_0016 Timer channel 3 register high (TIMC3H) S
0x00ce_0017 0x00cf_0017 Timer channel 3 register low (TIMC3L) S
0x00ce_0018 0x00cf_0018 Pulse accumulator control register (TIMPACTL) S
0x00ce_0019 0x00cf_0019 Pulse accumulator flag register (TIMPAFLG) S
0x00ce_001a 0x00cf_001a Pulse accumulator counter register high (TIMPACNTH) S
0x00ce_001b 0x00cf_001b Pulse accumulator counter register low (TIMPACNTL) S
0x00ce_001c 0x00cf_001c Reserved (2) —
0x00ce_001d 0x00cf_001d Timer port data register (TIMPORT) S
0x00ce_001e 0x00cf_001e Timer port data direction register (TIMDDR) S
0x00ce_001f 0x00cf_001f Timer test register (TIMTST) S
1. S = CPU supervisor mode access only.
2. Writes have no effect, reads return 0s, and the access terminates without a transfer error exception.
MMC2107 – Rev. 2.0
Technical Data
MOTOROLA Timer Modules (TIM1 and TIM2) 299
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