MMC2107 - Freescale Semiconductor

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Timer Modules (TIM1 and TIM2) Freescale Semiconductor, Inc. 15.9 Reset Reset initializes the timer registers to a known startup state as described in the 15.7 Memory Map and Registers. 15.10 Interrupts Table 15-8 lists the interrupt requests generated by the timer. nc... Freescale Semiconductor, I 15.10.1 Timer Channel Interrupts (CxF) NOTE: Table 15-8. Timer Interrupt Requests Interrupt Request Flag Enable Bit Channel 3 IC/OC C3F C3I Channel 2 IC/OC C2F C2I Channel 1 IC/OC C1F C1I Channel 0 IC/OC C0F C0I PA overflow PAOVF PAOVI PA input PAIF PAI Timer overflow TOF TOI A channel flag is set when an input capture or output compare event occurs. Clear a channel flag by writing a 1 to it. When the fast flag clear all bit, TFFCA, is set, an input capture read or an output compare write clears the corresponding channel flag. TFFCA is in timer system control register 1 (TIMSCR1). When a channel flag is set, it does not inhibit subsequent output compares or input captures Technical Data MMC2107 – Rev. 2.0 326 Timer Modules (TIM1 and TIM2) MOTOROLA For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc. Timer Modules (TIM1 and TIM2) Interrupts 15.10.2 Pulse Accumulator Overflow (PAOVF) PAOVF is set when the 16-bit pulse accumulator rolls over from $FFFF to $0000. If the PAOVI bit in TIMPACTL is also set, PAOVF generates an interrupt request. Clear PAOVF by writing a 1 to it. NOTE: When the fast flag clear all enable bit, TFFCA, is set, any access to the pulse accumulator counter registers clears all the flags in TIMPAFLG. 15.10.3 Pulse Accumulator Input (PAIF) nc... Freescale Semiconductor, I NOTE: 15.10.4 Timer Overflow (TOF) NOTE: PAIF is set when the selected edge is detected at the PAI pin. In event counter mode, the event edge sets PAIF. In gated time accumulation mode, the trailing edge of the gate signal at the PAI pin sets PAIF. If the PAI bit in TIMPACTL is also set, PAIF generates an interrupt request. Clear PAIF by writing a 1 to it. When the fast flag clear all enable bit, TFFCA, is set, any access to the pulse accumulator counter registers clears all the flags in TIMPAFLG. TOF is set when the timer counter rolls over from $FFFF to $0000. If the TOI bit in TIMSCR2 is also set, TOF generates an interrupt request. Clear TOF by writing a 1 to it. When the timer channel 3 registers contain $FFFF and TCRE is set, TOF never gets set even though the timer counter registers go from $FFFF to $0000. When the fast flag clear all bit, TFFCA, is set, any access to the timer counter registers clears timer flag register 2. The TFFCA bit is in timer system control register 1 (TIMSCR1). When TOF is set, it does not inhibit future overflow events. MMC2107 – Rev. 2.0 Technical Data MOTOROLA Timer Modules (TIM1 and TIM2) 327 For More Information On This Product, Go to: www.freescale.com
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MMC2107 - Freescale Semiconductor

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