MMC2107 - Freescale Semiconductor

Freescale Semiconductor, Inc.
Programmable Interrupt Timer Modules (PIT1 and PIT2)
Memory Map and Registers
14.6.2.1 PIT Control and Status Register
Address: PIT1 — 0x00c8_0000 and 0x00c8_0001
PIT2 — 0x00c9_0000 and 0x00c9_0001
Bit 15 14 13 12 11 10 9 Bit 8
Read: 0 0 0 0
Write:
PRE3 PRE2 PRE1 PRE0
Reset: 0 0 0 0 0 0 0 0
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Read: 0
Write:
Bit 7 6 5 4 3 2 1 Bit 0
PDOZE PDBG OVW PIE PIF RLD EN
Reset: 0 0 0 0 0 0 0 0
= Writes have no effect and the access terminates without a transfer error exception.
Figure 14-2. PIT Control and Status Register (PCSR)
PRE[3:0] — Prescaler Bits
The read/write PRE[3:0] bits select the system clock divisor to
generate the PIT clock as Table 14-2 shows.
To accurately predict the timing of the next count, change the
PRE[3:0] bits only when the enable bit (EN) is clear. Changing the
PRE[3:0] resets the prescaler counter. System reset and the loading
of a new value into the counter also reset the prescaler counter.
Setting the EN bit and writing to PRE[3:0] can be done in this same
write cycle. Clearing the EN bit stops the prescaler counter.
PDOZE — Doze Mode Bit
The read/write PDOZE bit controls the function of the PIT in doze
mode. Reset clears PDOZE.
1 = PIT function stopped in doze mode
0 = PIT function not affected in doze mode
When doze mode is exited, timer operation continues from the state
it was in before entering doze mode.
MMC2107 – Rev. 2.0
Technical Data
MOTOROLA Programmable Interrupt Timer Modules (PIT1 and PIT2) 285
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