MMC2107 - Freescale Semiconductor

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Non-Volatile Memory FLASH (CMFR) Freescale Semiconductor, Inc. 9.7.1.1 CMFR Module Configuration Register The CMFR module configuration register (CMFRMCR) controls operation of the CMFR array and BIU. Address: 0x00d0_0000 through 0x00d0_0003 Bit 31 30 29 28 27 26 25 Bit 24 Read: Write: FSTOP FDBG 0 EME SIE LOCKCTL DIS RSVD24 nc... Freescale Semiconductor, I Reset: 0 0 0 Note 1 0 0 Note 1 0 Read: Write: Bit 23 22 21 20 19 18 17 Bit 16 SUPV7 SUPV6 SUPV5 SUPV4 SUPV3 SUPV2 SUPV1 SUPV0 Reset: 1 1 1 1 1 1 1 1 Read: Write: Bit 15 14 13 12 11 10 9 Bit 8 DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 Reset: 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 Bit 0 Read: PROTECT7 PROTECT6 PROTECT5 PROTECT4 PROTECT3 PROTECT2 PROTECT1 PROTECT0 Write: Reset: 1 1 1 1 1 1 1 1 = Writes have no effect and the access terminates without a transfer error exception. Notes: 1. Reset state is determined during reset configuration. Figure 9-3. CMFR Module Configuration Register (CMFRMCR) Technical Data MMC2107 – Rev. 2.0 188 Non-Volatile Memory FLASH (CMFR) MOTOROLA For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc. Non-Volatile Memory FLASH (CMFR) Registers and Memory Map FSTOP — FLASH Stop Enable Bit The read-always FSTOP bit causes the CMFR to enter a low-power stop mode. Writing has no effect if SES = 1. When FSTOP is set, the BIU continues to operate to allow accesses to CMFRMCR. Accesses to other registers are terminated with bus error. Accesses to the array are ignored. To prevent unpredictable behavior, change the FSTOP bit in a separate write operation. 1 = CMFR in low-power stop mode 0 = CMFR in normal mode nc... Freescale Semiconductor, I FDBG — FLASH Debug Enable Bit The read/write FDBG bit determines whether the set-once LOCKCTL bit is writable when the chip is in debug mode. Writing to the FDBG bit must occur before the LOCKCTL bit is writable. 1 = Debug mode enabled 0 = Debug mode disabled EME — Emulation Enable Bit The read-always EME bit enables the CMFR to enter emulation mode. EME is writable when the LOCKCTL and DIS bits are set. During emulation mode the CMFR terminates array access cycles, but does not drive data. Array data can be emulated by reading an external memory, and on-page/off-page timing is the same as in non-emulation mode. Note that write accesses to the array space are the same as normal mode. 1 = Emulation mode enabled 0 = Emulation mode disabled For more information about emulation operation see 9.8.7 Emulation Operation. SIE — Shadow Information Enable Bit The read-always SIE bit selects the shadow information row. SIE is write-protected when the ERASE bit is clear and the SES bit is set. When SIE is set and an array location is read using supervisor data, the shadow information is read from a location determined by the column, 32 byte read page select, and word addresses of the access. Accessing the control block registers accesses the registers and not the shadow information. 1 = Shadow information enabled; normal array access disabled 0 = Shadow information disabled; normal array access enabled MMC2107 – Rev. 2.0 Technical Data MOTOROLA Non-Volatile Memory FLASH (CMFR) 189 For More Information On This Product, Go to: www.freescale.com
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