MMC2107 - Freescale Semiconductor

Freescale Semiconductor, Inc.
Clock Module
Memory Map and Registers
RFD[2:0] — Reduced Frequency Divider Field
The binary value written to RFD[2:0] is the PLL frequency divisor. See
Table 10-3. Changing RFD[2:0] does not affect the PLL or cause a
relock delay. Changes in clock frequency are synchronized to the
next falling edge of the current system clock. To avoid surpassing the
allowable system operating frequency, write to RFD[2:0] only when
the LOCK bit is set.
nc...
Freescale Semiconductor, I
NOTE:
NOTE:
NOTE:
In external clock mode, the RFD[2:0] bits have no effect.
See Table 10-6.
LOCEN — Loss of Clock Enable Bit
The LOCEN bit enables the loss of clock function. LOCEN does not
affect the loss of lock function.
1 = Loss of clock function enabled
0 = Loss of clock function disabled
In external clock mode, the LOCEN bit has no effect.
DISCLK — Disable CLKOUT Bit
The DISCLK bit determines whether CLKOUT is driven. Setting the
DISCLK bit holds CLKOUT low.
1 = CLKOUT disabled
0 = CLKOUT enabled
FWKUP — Fast Wakeup Bit
The FWKUP bit determines when the system clocks are enabled
during wakeup from stop mode.
1 = System clocks enabled on wakeup regardless of PLL lock
status
0 = System clocks enabled only when PLL is locked or operating
normally
When FWKUP = 0, if the PLL or OSC is enabled and unintentionally lost
in stop mode, the PLL wakes up in self-clocked mode or reference clock
mode depending on the clock that was lost.
In external clock mode, the FWKUP bit has no effect on the wakeup
sequence.
MMC2107 – Rev. 2.0
Technical Data
MOTOROLA Clock Module 229
For More Information On This Product,
Go to: www.freescale.com